Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency
AssigneeIntel Corporation
InventorsNazar A. Zaidi, Michael J. Morrison, Elango Ganesan
Life of this patent
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Abstract
A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.
Claims21
A method for scheduling instructions for execution, comprising:
- receiving a plurality of instructions;
- selecting a first instruction whose execution can cause an exception;
- assigning a post-ready latency to a second instruction that follows the first instruction;
- and
- scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.
A method for scheduling instructions for execution, comprising:
- receiving a plurality of instructions;
- selecting a producer instruction whose execution can potentially cause an exception;
- selecting a consumer instruction that receives at least one operand from the producer instruction;
- assigning a post-ready latency to the consumer instruction;
- and
- scheduling for execution by at least one execution unit the producer instruction and the consumer instruction with the execution of the consumer instruction following the execution of the producer instruction by an amount of time at least equal to the post-ready latency of the consumer instruction.
An apparatus for scheduling instructions for execution in a processor, comprising an instruction decode and rename unit adapted to receive a plurality of instructions and to assign post-ready latencies to the instructions to allow proper exception handling by the processor.
An apparatus for scheduling instructions for execution, comprising:
- means for fetching a plurality of instructions from a memory;
- means for assigning post-ready latency to any instruction that receives at least one input from at least one instruction that can cause an exception;
- means for scheduling each instruction for execution;
- and
- means for executing each instruction.
An apparatus for scheduling instructions for execution, comprising:
- an instruction fetch unit;
- an instruction decode and rename unit operably associated with the instruction fetch unit and adapted to assign post-ready latencies to instructions that receive at least one input from at least one instruction that can cause an exception;
- a scheduler operably associated with the instruction decode and rename unit;
- and
- at least one execution unit operably associated with the scheduler.
Dependencies are inferred from the claim text.