System and method for recovering a microprocessor from a locked bus state

A method for recovering from a locked bus state in a data processing system, the method comprising:

• (a) beginning execution of software instructions by a central processing unit (CPU) within the data processing system, wherein the software instructions are communicated to the CPU by a bus;
• (b) generating a watchdog timer interrupt in response to a first time out condition occurring in a watchdog timer, the watchdog timer being internal to the data processing system;
• (c) attempting to handle the watchdog timer interrupt within the data processing system;
• (d) generating, if the watchdog timer interrupt is not properly handled in step (c), a watchdog bus termination signal in response to a second time out condition occurring in the watchdog timer;
• (e) setting a watchdog status bit internal to the data processing system in response to an assertion of the watchdog bus termination signal in step (d);
• and
• (f) attempting to terminate at least one bus cycle in response to the assertion of the watchdog bus termination signal in an attempt to recover the bus from a locked bus state.

A data processing system comprising:

• a central processing unit adapted to be coupled through a bus to memory;
• a watchdog timer coupled to the central processing unit;
• and
• a watchdog control register coupled to the watchdog timer and having a plurality of bits comprising:
• a first enable bit for enabling or disabling use of the watchdog timer within the data processing system;
• a second enable bit for selecting a mode of operation of the watchdog timer when the watchdog timer is enabled by the first enable bit;
• at least one bit for determining a time period from a watchdog timer reset to a watchdog timer time-out for the watchdog timer;
• and
• a status bit which is activated when the watchdog timer generates a bus transfer termination signal.