Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
AssigneeIntel Corporation
InventorsWilliam S. Wu, Peter D. MacWilliams, Stephen Pawlowski, Muthurajan Jayakumar
Life of this patent
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Abstract
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.
Claims9
A method for efficient memory access in a computer system that includes an agent coupled to a chipset via a bus, the method comprising:
- issuing a first ordered transaction on the bus;
- deferring processing of the first ordered transaction;
- asserting a visibility signal by the chipset;
- and
- issuing a second ordered transaction on the bus responsive to the visibility signal before the first ordered transaction is completed.
A system comprising:
- a bus;
- a chipset coupled to the bus, the chipset being configured to generate a defer signal and a visibility signal;
- and an agent coupled to the bus and the chipset, wherein the agent is configured to:
- (I) issue a first ordered transaction on the bus;
- (ii) defer processing the first ordered transaction in response to the defer signal;
- (iii) issue a second ordered transaction on the bus in response to the visibility signal before the first ordered transaction is complete.
Dependencies are inferred from the claim text.