Method and circuit for detecting address limit violations in a microprocessor-based computer

A method of checking for address limit violations in a microprocessor based computer comprising:

• providing a linear address, a base address, and a logical limit to a full adder circuit;
• computing a plurality of sum bits and a plurality of carry bits from said linear address, said base address, and said logical limit with said full adder circuit;
• providing said plurality of sum bits and said plurality of carry bits to a definite limit violation detection circuit, wherein said definite limit violation detection circuit produces a definite limit violation signal in response to said plurality of sum bits and said plurality of carry bits;
• and
• providing said plurality of sum bits and said plurality of carry bits to a potential limit violation detection circuit, wherein said potential limit violation detection circuit produces a potential limit violation signal in response to said plurality of sum bits and said plurality of carry bits;
• wherein said potential limit violation detection circuit complements a least significant bit of said plurality of sum bits to produce a least significant bit of a result.

In a microprocessor based computer system, an address limit violation detection circuit, comprising:

• a full adder circuit adapted to receive a linear address, a base address, and a limit value, and further adapted to produce a plurality of sum bits and carry bits in response thereto;
• a definite limit violation detection circuit adapted to receive said plurality of sum bits and carry bits from said full adder circuit and further adapted to produce a first signal in response thereto wherein said first signal is indicative of whether said linear address is greater than the sum of said base address and said limit;
• and
• a potential limit violation detection circuit adapted to receive said plurality of sum bits and carry bits from said full adder circuit and further adapted to produce a second signal in response thereto wherein said second signal is indicative of whether said linear address is equal to the sum of said base address and said limit value;
• wherein said linear address, said base address, and said limit value each comprise n bits;
• wherein said potential limit violation detection circuit includes an inverter for inverting a least significant bit of said plurality of sum bits to produce a least significant bit of an n-bit result.

In a microprocessor based computer system, an address limit violation detection circuit, comprising:

• a full adder circuit adapted to receive a linear address, a base address, and a limit value, and further adapted to produce a plurality of sum bits and carry bits in response thereto;
• a definite limit violation detection circuit adapted to receive said plurality of sum bits and carry bits from said full adder circuit and further adapted to produce a first signal in response thereto wherein said first signal is indicative of whether said linear address is greater than the sum of said base address and said limit;
• and
• a potential limit violation detection circuit adapted to receive said plurality of sum bits and carry bits from said full adder circuit and further adapted to produce a second signal in response thereto wherein said second signal is indicative of whether said linear address is equal to the sum of said base address and said limit value;
• wherein said full adder circuit includes an initial stage for producing a one's complement representation of said base address and said limit value.