Microprocessor having combined shift and rotate circuit

An arithmetic operation unit for performing shift/rotate operations on operands of any of a plurality of sizes between 1 and 4 bytes, comprising:

• an 8-bit shift and rotate circuit having an input for receiving an operand sized between 1 and 4 bytes and an output, said 8-bit shift and rotate circuit selectively performing shift/rotate/pass operations on 4 byte sized operands and pre-processing operations which replicate 1 byte sized operands into 2 byte sized operands;
• a 16-bit shift and rotate circuit having an input coupled to said output of said 8-bit shift and rotate circuit and an output, said 16-bit shift and rotate circuit selectively performing shift/rotate/pass operations on 4 byte sized operands and pre-processing operations which expand 2 byte sized operands into 4 byte sized operands;
• a 1-bit shift and rotate circuit having an input coupled to said output of said 16-bit shift and rotate circuit and an output, said 1-bit shift and rotate circuit selectively performing shift/rotate/pass operations on 4 byte sized operands;
• a 2-bit shift and rotate circuit having an input coupled to said output of said 1-bit shift and rotate circuit and an output, said 2-bit shift and rotate circuit selectively performing shift/rotate/pass operations on 4 byte sized operands;
• and
• a 4-bit shift and rotate circuit having an input coupled to said output of said 2-bit shift and rotate circuit and an output, said 4-bit shift and rotate circuit selectively performing shift/rotate/pass operations on said 4 byte sized operands.

A microprocessor, comprising:

• a register for holding an operand of any of a plurality of sizes between 1 and N bytes;
• and
• an execution unit for performing arithmetic operations on said operand;
• said execution unit including:
• a first n-bit internal bus;
• a second n-bit internal bus;
• and
• a multiple stage, shift and rotate circuit having an input coupled to said first n-bit internal bus and an output coupled to said second n-bit internal bus;
• said multiple stage shift and rotate circuit configured to perform (1 to (n-1))-bit shift/rotate/pass operations on (8 to n)-bit operands propagated thereto via said first n-bit internal bus;
• wherein at least one stage of said multiple stage shift and rotate circuit selectively performs shift/rotate/pass operations on n-bit operands and replicates operands sized less than n-bit operands to produce n-bit sized operands.

A computer, comprising:

• a system bus;
• a memory subsystem;
• and
• a microprocessor;
• said memory subsystem and said microprocessor coupled to said system bus for bi-directional exchanges of address, data and control signals therebetween;
• said microprocessor including:
• a multiple stage, shift and rotate circuit configured to perform (1 to 31)-bit shift/rotate/pass operations on (8 to 32)-bit operands propagated thereto;
• wherein:
• a first stage of said multiple stage shift and rotate circuit is an 8-bit shift and rotate unit which selectively performs 8-bit shift/rotate/pass operations on 32-bit operands and replicate 8-bit operands into 16-bit operands;
• and
• a second stage of said multiple stage shift and rotate circuit is a 16-bit shift and rotate circuit which selectively performs 16-bit shift/rotate/pass operations on 32-bit operands and replicate 16-bit operands into 32-bit operands.