Built in shelf test method and apparatus for booth multipliers

A Built In Self Test (BIST) device comprising:

• a regular arithmetic structure to be tested, wherein the regular arithmetic structure uses carry propagate adder arrays to add partial products and wherein the regular arithmetic structure is comprised of at least two cell means that perform an arithmetic operation;
• Test Pattern Generator (TPG) means externally coupled to the regular arithmetic structure, wherein the TPG is operable to generate a set of test vectors to enable external testing of a substantial portion of all inputs to the cells of the regular arithmetic structure;
• and
• multiplexer means coupled to an output of the TPG means and an input to the regular arithmetic structure.

A logic test article comprising:

• a regular arithmetic structure to be tested, wherein the regular arithmetic structure uses carry propagate adder arrays to add partial products and wherein the regular arithmetic structure is comprised of at least two cells means that perform arithmetic operations;
• Test Pattern Generator (TPG) means externally coupled to the regular arithmetic structure, wherein the TPG is operable to generate a set of test vectors to enable external testing of a substantial portion of all inputs to the cells of the regular arithmetic structure;
• and
• multiplexer means coupled to an output of the TPG means and an input to the regular arithmetic structure.

A method of self testing a regular arithmetic structure comprising the steps of:

• providing a regular arithmetic structure to be tested, wherein the regular arithmetic structure carry propagates adder arrays to add partial products and wherein the regular arithmetic structure includes at least two cells means that perform arithmetic operations;
• externally coupling Test Pattern Generator (TPG) means to the regular arithmetic structure;
• coupling a multiplexer means to the TPG to provide an input to the regular arithmetic structure;
• and
• generating from the TPG means a set of test vectors to enable external testing of a substantial portion of all inputs to the cells of the regular arithmetic structure.