Method for testing asynchronous circuits

A method for testing an asynchronous circuit comprising the steps of:

• constructing a Synchronous Test Model for the asynchronous circuit wherein said asynchronous circuit does not have a pre-specified clock by constructing an input logic block for the asynchronous circuit, by constructing an output logic block for the asynchronous circuit, and by constructing an input/output signal flow generator for the asynchronous circuit;
• generating a test for the Synchronous Test Model;
• translating, without requiring any modification of the asynchronous circuit, a set of patterns for the Synchronous Test Model to the asynchronous circuit;
• creating a target fault list that contains only faults in the asynchronous circuit;
• and
• validating the translated patterns by fault simulation on the asynchronous circuit;
• where said output logic block includes:
• an AND gate having two inputs and a single output such that when one of the inputs is at a predetermined high level, and the other input is at a particular low level, the output is at a level equal to the particular low level of the other input, otherwise the output remains unchanged.

A method for testing an asynchronous circuit comprising the steps of:

• constructing a Synchronous Test Model for the asynchronous circuit wherein said asynchronous circuit does not have a pre-specified clock by, constructing an input logic block for the asynchronous circuit, by constructing an output logic block for the asynchronous circuit, and by constructing an input/output signal flow generator for the asynchronous circuit;
• generating a test for the Synchronous Test Model;
• translating, without requiring any modification of the asynchronous circuit, a set of patterns for the Synchronous Test Model to the asynchronous circuit;
• creating a target fault list that contains only faults in the asynchronous circuit;
• and
• validating the translated patterns by fault simulation on the asynchronous circuit,
• where said input/output signal flow generator includes:
• an AND gate having a plurality of inputs and an output;
• and
• a modulo-n counter having a plurality of outputs, wherein each one of said outputs is connected to a respective one of said AND inputs such that said modulo-n counter outputs are all at a predetermined high level once every n cycles and said AND output is at the predetermined high level once every n cycles.