Efficient on-pitch scannable sense amplifier

An apparatus comprising:

• a microprocessor including a memory;
• said memory including a plurality of sense amplifiers, each of said sense amplifiers including a pair of cross coupled transistors, said memory including,
• a plurality of first polysilicon structures extending in a horizontal direction along first row in a reference plane generally parallel to a surface of a semiconductor substrate, each of said first polysilicon structures extending generally in a vertical direction parallel to said surface;
• a first active region extending in a horizontal direction parallel to said surface and intersecting said first polysilicon structures, thereby forming first transistors having a channel of a first conductivity type, each of said first transistors being a first transistor of said pair of cross coupled transistors;
• a plurality of second polysilicon structures extending in said horizontal direction along a second row parallel to said surface, each of said second polysilicon structures extending generally in said vertical direction and parallel to said surface, and wherein said second row is disposed vertically below said first row in said plane;
• a second active region extending horizontally in a direction parallel to said surface and intersecting said second polysilicon structures, thereby forming second transistors having a channel of said first conductivity type, each of said second transistors being a second transistor of said pair of cross coupled transistors;
• and
• a plurality of third polysilicon structures extending in a horizontal direction parallel to said surface, each of said third polysilicon structures extending parallel to said surface in a vertical direction, each of said third polysilicon structures being disposed between two of said first polysilicon structures and two of said second polysilicon structures, said third polysilicon structures extending sufficiently in a vertical direction to intersect said first and second active regions, thereby forming respectively a third and fourth group of transistors having a channel region of said first conductivity type, said third and fourth group of transistors respectively coupling adjacent ones of said first and second groups of transistors.

A method in a semiconductor memory device having a plurality of sense amplifiers, wherein each of said sense amplifiers includes a pair of cross coupled transistors, said method comprising:

• providing a plurality of first polysilicon structures extending in a horizontal direction along first row in a reference plane generally parallel to a surface of a semiconductor substrate, each of said first polysilicon structures extending generally in a vertical direction parallel to said surface;
• providing a first active region extending in a horizontal direction parallel to said surface and intersecting said first polysilicon structures, thereby forming first transistors having a channel of a first conductivity type, each of said first transistors being a first transistor of said pair of cross coupled transistors;
• providing a plurality of second polysilicon structures extending in said horizontal direction along a second row parallel to said surface, each of said second polysilicon structures extending generally in said vertical direction and parallel to said surface, and wherein said second row is disposed vertically below said first row in said plane;
• providing a second active region extending horizontally in a direction parallel to said surface and intersecting said second polysilicon structures, thereby forming second transistors having a channel of said first conductivity type, each of said second transistors being a second transistor of said pair of cross coupled transistors;
• providing a plurality of third polysilicon structures extending in a horizontal direction parallel to said surface, each of said third polysilicon structures extending parallel to said surface in a vertical direction, each of said third polysilicon structures being disposed between two of said first polysilicon structures and two of said second polysilicon structures, said third polysilicon structures extending sufficiently in a vertical direction to intersect said first and second active regions, thereby forming respectively a third and fourth group of transistors having a channel region of said first conductivity type, said third and fourth group of transistors respectively coupling adjacent ones of said first and second groups of transistors.