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US 5,958,074 AGranted
Data processor having data bus and instruction fetch bus provided separately from each other
AssigneeNEC Corporation
InventorHideki Sugimoto
Life of this patent
Estimating the term…
Abstract
A data processor has an internal data bus and an instruction fetch bus provided separately from each other. When a data-read operation mode is designated, data stored in an internal read only memory are read out onto both the internal data bus and the instruction fetch bus, and the data on these buses are then subject to an operation by an execution unit to check the coincidence therebetween, the comparison resultant signal being transferred to the outside.
Claims3
A data processing apparatus having a normal processing mode and a test mode, comprising:
- a memory storing data;
- a first bus transferring data from said memory in said test mode;
- a second bus transferring data from said memory in said test mode;
- a decoder receiving said data present on said first bus and transferring said data to a node in said test mode;
- and
- an executing unit comparing said data present on said second bus to said data present on said node and out-putting a result of said comparison in said test mode.
3 more elements
Dependencies are inferred from the claim text.