Computer-system processor-to-memory-bus interface having repeating-test-event generation hardware

Abstract

A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator. The timing generator can include a down counter and a register for holding a value to be entered into the counter upon initialization and reset. So that cache error-correction logic can be tested, a cache manager includes a cache-error generator that can generate cache errors at times determined by said timing generator. The test-event hardware permits system events of interest to be repeatedly generated during a test procedure without repeated intervention by a test program. The hardware test-event generation simplifies test program design and allows faster testing throughput.

Dependencies are inferred from the claim text.