Remote checkpoint memory system and protocol for fault-tolerant computer system

A computer implemented method for use with at least three computers, wherein each of the computers, except one spare computer, performs data processing tasks with a data communications network coupled to each of the computers such that the plurality of computers are connected in a logical ring and wherein each computer includes a processor having a cache, internal registers and input/output event queue and connected to a main memory and a write buffer coupled to the main memory, the method comprising:

• in each computer, capturing data written to the main memory by the processor;
• in each computer, flushing the cache, internal registers and input/output event queue to the main memory;
• copying data from the write buffer to the main memory of an adjacent computer in the logical ring at periodic checkpoints;
• and
• upon failure of one of the computers that perform data processing tasks, performing the data processing tasks of the computers that perform data processing tasks using functional computers of the at least three computers, including using the spare computer, without loss of data.

A computer system for providing fault tolerance having first and second computers, each of the first and second computers having a processor with a cache, internal registers and an input/output event queue, a main memory and a buffer memory, wherein the first computer includes:

• means for capturing data written to the main memory of the first computer;
• means for transferring the captured data to the buffer memory of the second computer;
• means for flushing the cache, internal registers and input/output event queue of the processor of the first computer such that data contained within the cache, internal registers and input/output event queue is written to the main memory of the first computer and to the buffer memory of the second computer;
• and wherein the second computer includes:
• means for copying data from the buffer memory of the second computer to the main memory of the second computer such that a checkpoint is established and the main memory of the second computer acts as a shadow memory of the main memory of the first computer.

A computer implemented process for use with a processor, a main memory subsystem coupled to the processor and including a primary memory element from which data is read and to which data is written by the processor and a write buffer, wherein the processor and the primary memory element are in a first computer and wherein the write buffer is in a second computer having a main memory subsystem and connected to the first computer by a communication link, and wherein the processor has a corresponding input/output subsystem which provides input/output events initiated by the processor, the process comprising:

• storing in the write buffer buffer data related to the data written by the processor to the primary memory element,
• queuing input/output events between checkpoints;
• flushing the queued events to the primary memory element when a checkpoint is to be established, whereby input/output events are captured in checkpoint data in the main memory subsystem of the second computer;
• and
• using the buffer data to ensure the existence of a consistent checkpoint state in the main memory subsystem of the second computer to which processing can resume without loss of data integrity or program continuity following a fault.

A computer system comprising:

• a first computer including:
• a processor for processing at least a first application and having a cache, internal registers and an input/output event queue,
• a main memory coupled to the processor and cache,
• a write buffer coupled to the main memory that captures data written to the main memory,
• means for transferring data in the write buffer to a second computer,
• wherein the processor includes means for flushing the cache, internal registers and input/output event queue to the main memory and means for issuing a checkpoint instruction to the second computer after flushing the cache, internal registers and input/output event queue;
• and
• the second computer including:
• means for receiving the data from the first computer,
• a main memory, and
• a buffer memory, coupled to the main memory of the second computer, that receives the data transferred from the write buffer of the first computer,
• wherein data stored in the buffer memory is transferred to the main memory of the second computer upon receipt of the checkpoint instruction from the first computer, such that the main memory of the second computer maintains a consistent state from which processing of the first application can be restarted.

A computer system comprising:

• at least three computers, wherein each of the computers except one spare computer performs data processing tasks;
• a data communications network coupled to each of the computers such that the plurality of computers are connected in a logical ring;
• wherein each computer includes:
• a processor having a cache, internal registers and input/output event queue and connected to a main memory and a write buffer coupled to capture data written to the main memory by the processor;
• means for flushing the cache, internal registers and input/output event queue to the main memory;
• means for copying data from the write buffer to the main memory of an adjacent computer in the logical ring at periodic checkpoints;
• and
• means, operative upon failure of one of the computers performing data processing tasks, for performing the data processing tasks of the failed computer on functional computers of the at least three computers including the spare computer without loss of data.

A method for providing fault tolerance in a computer system having first and second computers, each of the first and second computers having a processor with a cache, internal registers and an input/output event queue, a main memory and a buffer memory, the method including steps of:

• capturing data written to the main memory of the first computer;
• transferring the captured data to the buffer memory of the second computer;
• flushing the cache, internal registers and input/output event queue of the processor of the first computer such that data contained within the cache, internal registers and input/output event queue is written to the main memory of the first computer and to the buffer memory of the second computer;
• and
• copying data from the buffer memory of the second computer to the main memory of the second computer such that a checkpoint is established and the main memory of the second computer acts as a shadow memory of the main memory of the first computer.

A computer system comprising:

• a processor;
• a primary memory element from which data is read and to which data is written by the processor;
• a write buffer that monitors each time data is written to the primary memory element by the processor and stores buffer data related to the data written to the processor;
• wherein the processor and the primary memory element are in a first computer and wherein the write buffer is in a second computer connected to the first computer;
• wherein the processor has a corresponding input/output subsystem which provides input/output events initiated by the processor, wherein the processor comprises:
• means for queuing input/output events between checkpoints;
• means for flushing the queued events to the primary memory element when a checkpoint is to be established, whereby input/output events are captured in the buffer data in the write buffer;
• and
• means, using the buffer data, for ensuring the existence of a consistent checkpoint state in the second computer to which processing can resume without loss of data integrity or program continuity following a fault.