Method for precise architectural update in an out-of-order processor

In a processor that executes coded instructions, the processor including at least one execution unit generating out-of-order results and out-of-order condition codes affecting an architectural state of the processor, a method for maintaining precise architectural state of the processor comprising the steps of:

• providing a results buffer having a number of slots;
• providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer;
• assigning each live instruction in the processor a slot in the results buffer and the condition code buffer;
• storing each speculative result produced by the at least one execution unit in a unique slot in the results buffer;
• storing each speculative condition code produced by the at least one execution unit in a unique slot in the condition code buffer;
• repetitively identifying non-speculative slots based upon which slots in the results buffer and condition code buffer are no longer dependent on an unresolved branch;
• in response to identifying non-speculative slots, transferring results stored in non-speculative slots of the results buffer to an architectural result register, and transferring condition code stored in non-speculative slots of the condition code buffer to an architectural condition code register;
• and
• repetitively emptying slots storing results that are dependent on a mispredicted branch.

In a processor that executes coded instructions, the processor including at least one execution unit generating out-of-order results and out-of-order condition codes affecting an architectural state of the processor, a method for maintaining precise architectural state of the processor comprising the steps of:

• providing a results buffer having a number of slots within each of the at least one execution unit;
• providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer;
• assigning each live instruction in the processor a slot in the results buffer and the condition code buffer;
• storing each speculative result produced by the at least one execution unit in a unique slot in the results buffer;
• storing each speculative condition code produced by the at least one execution unit in a unique slot in the condition code buffer;
• repetitively identifying non-speculative slots based upon which slots in the results buffer and condition code buffer are no longer dependent on an unresolved branch;
• and
• in response to identifying non-speculative slots, transferring results stored in non-speculative slots of the results buffer to an architectural result register, and transferring condition code stored in non-speculative slots of the condition code buffer to an architectural condition code register.

In a processor that executes coded instructions, the processor including an integer execution unit and a floating point execution unit generating out-of-order results and out-of-order condition codes affecting an architectural state of the processor, a method for maintaining precise architectural state of the processor comprising the steps of:

• providing a first results buffer in the integer execution unit having a number of slots;
• providing a second results buffer in the floating point execution unit having a number of slots;
• providing a first condition code buffer having the same number of slots as the first results buffer, each slot in the first condition code buffer in one-to-one correspondence with a slot in the first results buffer;
• providing a second condition code buffer having the same number of slots as the second results buffer, each slot in the second condition code buffer in one-to-one correspondence with a slot in the second results buffer;
• assigning each live instruction in the processor a slot in a results buffer and a condition code buffer;
• storing each speculative result produced by the execution units in a unique slot in a results buffer;
• storing each speculative condition code produced by the execution units in a unique slot in a condition code buffer;
• repetitively identifying non-speculative slots based upon which slots in the results buffers and condition code buffers are no longer dependent on an unresolved branch;
• and
• in response to identifying non-speculative slots, transferring results stored in non-speculative slots of a results buffer to an architectural result register, and transferring condition code stored in non-speculative slots of a condition code buffer to an architectural condition code register.

In a processor that executes coded instructions and includes an integer execution unit and a floating point execution unit, at least one execution unit generating out-of-order results and out-of-order condition codes affecting an architectural state of the processor, a method for maintaining precise architectural state of the processor comprising the steps of:

• providing a single results buffer for both the integer execution unit and the floating point execution unit having a number of slots;
• providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer;
• assigning each live instruction in the processor a slot in the results buffer and the condition code buffer;
• storing each speculative result produced by the execution units in a unique slot in the results buffer;
• storing each speculative condition code produced by the execution units in a unique slot in the condition code buffer;
• repetitively identifying non-speculative slots based upon which slots in the results buffer and condition code buffer are no longer dependent on an unresolved branch;
• and
• in response to identifying non-speculative slots, transferring results stored in non-speculative slots of the results buffer to an architectural result register, and transferring condition code stored in non-speculative slots of the condition code buffer to an architectural condition code register.

In a processor that executes coded instructions, the processor including at least one execution unit generating out-of-order results and out-of-order condition codes affecting an architectural state of the processor, a method for maintaining precise architectural state of the processor comprising the steps of:

• providing a results buffer having a number of slots;
• providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer;
• assigning each live instruction in the processor a slot in the results buffer and the condition code buffer;
• executing a live instruction from a first program thread;
• executing a live instruction from a second program thread;
• storing each speculative result produced by the at least one execution unit in a unique slot in the results buffer;
• storing each speculative condition code produced by the at least one execution unit in a unique slot in the condition code buffer;
• repetitively identifying non-speculative slots based upon which slots in the results buffer and condition code buffer are no longer dependent on an unresolved branch;
• in response to identifying non-speculative slots, transferring results stored in non-speculative slots of the results buffer to an architectural result register, and transferring condition code stored in non-speculative slots of the condition code buffer to an architectural condition code register;
• and
• wherein the step of transferring results comprising the steps of;
• determining which program thread produced a result stored in an identified non-speculative slot;
• selecting one from among a plurality of architectural result registers based on the program thread determining step;
• selecting one from among a plurality of architectural condition code registers based on the program thread determining step;
• transferring results in the identified non-speculative slot to the selected one architectural result register;
• and
• transferring condition code in the non-speculative slot to the selected one architectural condition code register.