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US 5,958,042 AGranted
Grouping logic circuit in a pipelined superscalar processor
AssigneeSun Microsystems, Inc.
InventorMarc Tremblay
Life of this patent
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Abstract
A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.
Claims8
A central processing unit, comprising:
- a plurality of functional units, each functional unit adapted to execute an instruction;
- and
- a grouping logic circuit, including a number of pipeline stages and receiving, at each processor cycle, a group of instructions, said grouping logic circuit dispatching each of said instructions to be executed by one of said fictional units,
- wherein said grouping logic circuit derives a state vector for a group of instructions received at a first processor cycle based on a number of state vectors derived for groups of instructions received in a number of processor cycles immediately preceding said first processor cycle, said number of processor cycles being equal to said number of pipeline stages.
1 more element
Dependencies are inferred from the claim text.