Latency prediction in a pipelined microarchitecture

A method for executing a first instruction and a second instruction in a processor, the second instruction using a result of the first instruction,

• the processor including an instruction cache, the instruction cache storing the first instruction and a latency prediction bit associated with the first instruction,
• the processor including an instruction issue unit, coupled to the instruction cache,
• the processor including a functional unit, coupled to the instruction issue unit, comprising the steps of:
• determining if the first instruction is of a particular instruction type;
• and
• if the first instruction is of said particular instruction type, determining if the latency prediction bit is cleared, and,
• if the latency prediction bit is cleared,
• issuing the first instruction to the functional unit,
• executing the first instruction in the functional unit,
• issuing the second instruction a first period of time after issuing the first instruction,
• determining if the result was not available for use by the second instruction prior to the execution of the second instruction, and if the result was not available prior to the execution of said second instruction,
• re-issuing at least the first instruction and
• setting the latency prediction bit, and,
• if the latency prediction bit is set,
• issuing the first instruction to the functional unit,
• executing the first instruction in the functional unit,
• issuing the second instruction a second period of time after issuing the first instruction,
• determining if the result was available for use by the second instruction within said first period of time of issuing the first instruction, and,
• clearing the latency prediction bit, if the result was available for use by the second instruction within said first period of time of issuing the first instruction.

A computer system, said computer system comprising:

• a bus;
• a memory, coupled to said bus;
• and
• a processor, coupled to said bus, including:
• an instruction memory having a plurality of entries, a latency prediction bit and a first instruction being stored in one of said plurality of entries;
• an instruction issue unit, coupled to said instruction memory, said instruction issue unit configured to issue a second instruction a period of time after issuing said first instruction, said period of time being determined at least in part by a value of said latency prediction bit;
• a first functional unit, coupled to said instruction issue unit and configured to execute said first and said second instructions;
• and
• control logic, coupled to said first functional unit and said instruction memory, configured to cause said latency prediction bit to assume, upon execution of at least said first instruction,
• a value that indicates said period of time is of a first duration, if a result of said first instruction was not available prior to a point in time when said result was needed for execution of said second instruction, and
• a value that indicates said period of time is of a second duration, if said result was available prior to said point in time.