Adaptive stream buffers
AssigneeDigital Equipment Corporation
InventorNorman P. Jouppi
Life of this patent
Estimating the term…
Abstract
The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.
Claims11
A method for prefetching data to a computer readable memory for possible use by a processor, the method comprising the steps of:
- a) providing a table for storing unproductive prefetch instruction addresses;
- b) for each memory reference instruction issuino from the processor that encounters a cache miss, performing the following steps:
- i) deternining whether an instruction address of the issued instruction matches any of the unproductive prefetch instruction addresses stored in the table;
- ii) selectively allocating the computer readable memory to prefetch data only when the instruction address of the issued instruction does not match any of the unproductive prefctch instruction addresses stored in the table;
- iii) determining whether data prefetched for the issued instruction is productive;
- and
- iv) selectively storing the instruction address of the issued instruction in the table as an unproductive prefetch instruction address only when data prefetched for the issued instruction is not productive.
An apparatus for prefetching data to a computer readable memory for possible use by a processor, the apparatus comprising:
- a processor, the processor periodically issuing instructions;
- a main memory;
- a computer readable memory for prefetching data from the main memory in response to a memory reference instruction issued from the processor that encounters a cache miss, the instruction having an instruction address;
- a table for storing the instruction address of the instruction as an unproductive prefetch instruction address when it is determined that the data prefetched to the computer readable memory was not used;
- an instruction-specific prefetch avoidance unit connected to the computer readable memory, the processor, and the table for preventing the computer readable memory from prefetching data in response to any subsequent instruction having an instruction address that matches an unproductive prefetch instruction address stored in the table.
A system for adaptively managing stream buffers, the system comprising:
- means for periodically issuing instructions having instruction addresses;
- a main memory;
- means for allocating a plurality of stream buffers to prefetch data from the main memory in response to an instruction from the instruction issuing means;
- means for determining whether data has been productively prefetched in response to a particular instruction address from the instruction issuing means;
- and
- means, responsive to the means for determining whether data has been productively prefetched, for preventing the allocation of a stream buffer when the instruction issuing means subsequently issues instructions having the same instruction address as the particular instruction address;
- whereby a stream buffer is not allocated in response to a subsequent instruction when a previous prefetch for the instruction address of the subsequent instruction has not been productive.
Dependencies are inferred from the claim text.