US 5,958,038 A · Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation

Abstract

A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction.

Claims18

Dependent claims

A method of executing an instruction having first, second, and third and an operand specifier, wherein the instruction specifies a logic operation, the method comprising the steps of:

performing the specified logic operation on first and second values selected from among first and second registers, respectively, and a general purpose register file to produce a result, wherein the operand specifier specifies from where to select the first and second values;
storing the result of the logic operation in a location selected from among first and second memories and the general purpose register file as identified by the third operand and the operand specifier;
updating the first value in the first register according to the first operand, the updating occurring substantially concurrently with the performance of the specified logic operation;
and
updating the second value in the second register according to the second operand, the updating occuring substantially concurrently with the performance of the specified logic operation.

2 more elements

A media processor for executing an instruction specifying first, second, and third operands and an operand combination, the processor comprising:

first and second memories for holding data for use by the media processor;
first and second stream registers, respectively coupled to the first and second memories, for holding data addressed in the first and second memories;
an address register file having first and second groups of register sets, wherein registers in the first and second groups of register sets are adopted to respectively specify addresses in the first and second memories and addressing modes;
a general purpose register file having a plurality of general purpose registers for holding general purpose data;
and
a logic unit accepting first and second inputs selected from among the first and second stream registers, respectively, and the general purpose registers, and producing an output stored at a location selected from the general purpose register file and the first and second memories;
wherein the first and second inputs to the logic unit are selected by the operand combination and the output of the logic unit is stored at a location specified by the third operand and the opened combination;
wherein the first and second operands of the instruction respectively specify first and second register sets in the address register file;
and
wherein the first and second operands of the instruction respectively specify first and second general purpose registers in the general purpose register file.

7 more elements

A processor for processing an instruction, the processor having an address register file, a general purpose register file in communication with first and second memories, and a logic operation unit accepting first and second inputs, wherein the instruction comprises:

an operation field specifying a logic operation to perform on the first and second inputs to the logic operation unit;
a first field specifying a first operand, wherein the first operand is selected from between the address register file and the general purpose register file and is capable of updating the first input to the operation unit;
a second field specifying a second operand, wherein the second operand is selected from between the address register file and the general purpose register file and is capable of updating the second input to the logic operation unit;
and
a third field specifying a third operand indicating where to store a result of the logic operation, wherein the third operand is selected from among the general purpose register file and the first and second memories.

2 more elements

Dependencies are inferred from the claim text.

Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation

Life of this patent

Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation

Life of this patent

Abstract

Claims18