US 5,958,033 A · On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies

Abstract

Method and apparatus for controlling a computer bus having first and second bus slots and operable with a bus controller at first and second data transfer rates. When the computer bus is operating at the first data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled to the address/data pins of both of the first and second bus slots, and the control pins of the bus controller are coupled only to the control pins of the second bus slot. When the computer bus is operating at the second data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled only to the address/data pins of the first bus slot, and the control pins of the bus controller are coupled only to the control pins of the first bus slot. The second data transfer rate may be faster than the first data transfer rate.

Claims17

Dependent claims

A partitionable computer bus, comprising:

a bus controller;
a set of bus partitioning switches, each operable to make and break connections between left and right terminals responsive to an open/close signal;
circuitry for generating said open/close signal;
first and second bus slots;
a first bus section coupling said bus controller to said first bus slot and to the left terminals of said set of bus partitioning switches;
and
a second bus section coupling the right terminals of said set of bus partitioning switches to said second bus slot;
wherein the computer bus is operable at first and second data transfer rates, said first data transfer rate faster than said second data transfer rate;
and
wherein said circuitry for generating said open/close signal is operable to open said set of bus partitioning switches when the computer bus is operating at said first data transfer rate, and to close said set of bus partitioning switches when the computer bus is operating at said second data transfer rate.

7 more elements

A partitionable computer bus, comprising:

a bus controller having address/data signal nodes and control signal nodes;
first and second bus slots, each having address/data signal nodes and control signal nodes;
a set of address/data signal partitioning switches, said set of address/data signal partitioning switches having an address/data partition input, and each switch in said set of address/data signal partitioning switches operable to make and break connections between left and right terminals responsive to said address/data partition input;
a first set of control signal partitioning switches, said first set of control signal partitioning switches having a first control partition input, and each switch in said first set of control signal partitioning switches operable to make and break connections between left and right terminals responsive to said first control partition input;
and
a second set of control signal partitioning switches, said second set of control signal partitioning switches having a second control partition input, and each switch in said second set of control signal partitioning switches operable to make and break connections between left and right terminals responsive to said second control partition input;
wherein:
the address/data signal nodes of said bus controller are coupled to the address/data signal nodes of said first bus slot and to the left terminals of said set of address/data signal partitioning switches;
the right terminals of said set of address/data signal partitioning switches are coupled to the address/data signal nodes of said second bus slot;
the control signal nodes of said bus controller are coupled to the left terminals of both of said first and second sets of control signal partitioning switches;
the right terminals of said first set of control signal partitioning switches are coupled to the control signal nodes of said first bus slot;
and
the right terminals of said second set of control signal partitioning switches are coupled to the control signal nodes of said second bus slot.

10 more elements

Dependencies are inferred from the claim text.

On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies

Life of this patent

On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies

Life of this patent

Abstract

Claims17