Data processing and communicating system with high throughput peripheral component interconnect bus

A data processing system comprising:

• a first data processing sub-system including
• a memory for storing first pieces of information,
• a bus connected to said memory for propagating said first pieces of information from said memory, and
• a first component device connected to said bus, having a first priority and communicable through said bus with said memory;
• and
• a second data processing sub-system including
• a peripheral component interconnect bus for propagating said first pieces of information and second pieces of information,
• at least one second component device connected to said peripheral component interconnect bus and supplying said second pieces of information to said peripheral component interconnect bus, and
• a bus bridge circuit connected to said bus and said peripheral component interconnect bus, having a second priority lower than said first priority, a first temporary memory for storing said first pieces of information and assigning a right to use said peripheral component interconnect bus to said at least one second component device so as to allow said at least one second component device to transfer said second pieces of information to said peripheral component interconnect bus until a data transfer of said first pieces of information to said first temporary memory is completed, and a second temporary memory for storing said second pieces of information supplied through said peripheral component interconnect bus and transferring said second pieces of information therein to said memory so as to store said second pieces of information therein,
• wherein said at least one second component device has
• a first state machine requesting said right to use said peripheral component interconnect bus to said bus bridge circuit for receiving said first pieces of information supplied from said first temporary memory to said peripheral component interconnect bus when said bus bridge circuit assigns said right thereto, and
• a second state machine requesting said right independently on said first state machine for supplying said second pieces of information through said peripheral component interconnect bus to said second temporary memory when said bus bridge circuit assigns said right thereto.