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US 5,958,031 AGranted
Data transmitting/receiving device of a multiprocessor system and method therefor
AssigneeSamsung Electronics Co., Ltd.
InventorMyeong-Soo Kim
Life of this patent
Estimating the term…
Abstract
A data transmitting/receiving device and method for transmitting and receiving data between processors in a multiprocessor system. A data bus interconnecting a plurality of processors is separated into sub-buses, with each sub-bus associated with a separate processor. This architecture serves to increase bus occupation efficiency and thereby improve system performance, and it allows DPRAMs to be replaced with SRAMs to reduce the production cost of the system.
Claims17
A data communication device in a multiprocessor system, comprising:
- a data bus including a plurality of sub-buses, with each one of said plurality of sub-buses having a proximal end connected to a proximal end of every other one of said plurality of sub-buses and a distal end connected to one of a plurality of processors in said multiprocessor system;
- and
- a plurality of memory devices, with each one of said plurality of memory devices being connected to one of said plurality of sub-buses between said proximal end and said distal end as a local memory device for said processor connected to said sub-bus;
- wherein each one of said plurality of sub-buses provides data communication between said memory device connected to said sub-bus and said processor connected to said sub-bus, and between said memory device connected to said sub-bus and every other one of said plurality of sub-buses;
- said device further comprising a plurality of buffers, and wherein each one of said plurality of buffers is interposed at said proximal end of one of said plurality of sub-buses between said sub-bus and every other one of said plurality of sub-buses.
2 more elements
A data communication device in a multiprocessor system, comprising:
- a data bus including a plurality of sub-buses, with each one of said plurality of sub-buses having a proximal end connected to a proximal end of every other one of said plurality of sub-buses and a distal end connected to one of a plurality of processors in said multiprocessor system;
- and
- a plurality of memory devices, with each one of said plurality of memory devices being connected to one of said plurality of sub-buses between said proximal end and said distal end as a local memory device for said processor connected to said sub-bus;
- wherein each one of said plurality of sub-buses provides data communication between said memory device connected to said sub-bus and said processor connected to said sub-bus, and between said memory device connected to said sub-bus and every other one of said plurality of sub-buses;
- said device further comprising a control unit in control communication with each one of said plurality of processors, wherein said control unit is adapted to:
- assign an access priority to each one of said plurality of processors at each one of a predetermined sequence of access cycles;
- and
- accept, at each one of said predetermined sequence of access cycles, a request for access to one of said plurality of memory devices from a first one of said plurality of processors when said access priority of said first one of said plurality of processors is higher than said access priority of any other one of said plurality of processors requesting access at said access cycle.
5 more elements
A data communication device in a multiprocessor system, comprising:
- a data bus including a plurality of sub-buses, with each one of said plurality of sub-buses having a proximal end connected to a proximal end of every other one of said plurality of sub-buses and a distal end connected to one of a plurality of processors in said multiprocessor system;
- and
- a plurality of memory devices, with each one of said plurality of memory devices being connected to one of said plurality of sub-buses between said proximal end and said distal end as a local memory device for said processor connected to said sub-bus;
- wherein each one of said plurality of sub-buses provides data communication between said memory device connected to said sub-bus and said processor connected to said sub-bus, and between said memory device connected to said sub-bus and every other one of said plurality of sub-buses;
- and
- said device further comprising a plurality of buffers, and wherein each one of said plurality of buffers is interposed at said proximal end of one of said plurality of sub-buses between said sub-bus and every other one of said plurality of sub-buses;
- wherein each one of said plurality of memory devices is an SRAM.
4 more elements
A data communication method, comprising the steps of:
- assigning, in a multiprocessor system having said plurality of processors and a data bus interconnecting said plurality of processors, with said data bus including a plurality of sub-buses and with each one of said plurality of sub-buses connecting a memory device to said plurality of processors at a distal end of said sub-bus and to every other one of said plurality of sub-buses at a proximal end of sub-bus, an access priority to each one of said plurality of processors at each one of a predetermined sequence of access cycles;
- and
- storing, at one of said predetermined sequence of access cycles, requested data over a first one of said plurality of sub-buses to said memory device connected to said first sub-bus in response to a data request from said processor connected at said distal end of said first sub-bus and in accordance with said access priority assigned to said processor for said access cycle.
A data communication method, comprising the steps of:
- receiving, in a multiprocessor system having a plurality of processors and a data bus interconnecting said plurality of processors, said data bus including a plurality of sub-buses, each of said plurality of sub-busses connecting a memory device to said plurality of processors at a distal end of said sub-bus and to every other one of said plurality of sub-buses at a proximal end of sub-bus, a request by one of said processors to access said memory device;
- determining whether said sub-bus to said memory device is occupied;
- when said sub-bus to said memory device is not occupied, determining whether there is a simultaneous request from a second processor;
- and
- where there is not a simultaneous request from said second processor, assigning access priority to said first processor.
2 more elements
Dependencies are inferred from the claim text.