Direct memory access (DMA) via separate bus utilizing a buffer for connecting the bus to the memory during DMA mode and disconnecting it otherwise
AssigneeNEC Corporation
InventorSatoru Sonobe
Life of this patent
Estimating the term…
Abstract
To increase access speed, a single-chip computer system having a direct memory access (DMA) mode, includes a central processing unit (CPU) for executing instructions, a first bus connected to the CPU, a memory array connected to the first bus, for storing data, a buffer connected to the first bus, a second bus connected to the buffer, and a communication circuit, connected to the second bus, for receiving and outputting data. The buffer connects the first bus to the second bus when the DMA mode is executed, and disconnects the first bus from the second bus when the DMA mode is not executed.
Claims26
A computer system having a direct memory access (DMA) mode, comprising:
- a central processing unit (CPU) for executing instructions;
- a first bus connected to said CPU;
- a memory array, connected to said first bus, for storing data;
- a buffer connected to said first bus;
- a second bus connected to said buffer;
- a communication circuit, connected to said second bus, for receiving and outputting data;
- and
- a clock control circuit for generating a first clock signal when said DMA mode is not executed, and for stopping generation of said first clock signal when the DMA mode is executed,
- wherein said buffer connects said first bus to said second bus when said DMA is executed, and disconnects said first bus from said second bus when said DMA is not executed.
A computer system having a direct memory access (DMA) mode, comprising:
- a central processing unit (CPU) for executing instructions;
- a clock control circuit for supplying a first clock signal to said CPU;
- and
- an oscillation circuit for supplying a second clock signal to said clock control circuit,
- wherein said clock control circuit generates said first clock signal based on said second clock signal, outputs said first clock signal to said CPU when said DMA mode is not executed, and stops supplying said first clock signal to said CPU when said DMA mode is executed.
A clock control circuit for a direct memory access (DMA) mode in a computer system, comprising:
- means for generating a first clock signal when said DMA mode is not executed;
- means for stopping generating said first clock signal when said DMA mode is executed;
- and
- an oscillation circuit, coupled to said clock control circuit for supplying a second clock signal,
- wherein said clock control circuit generates said first clock signal based on said second clock signal, and said oscillation circuit continues outputting said second clock signal regardless of said DMA mode being executed, and
- wherein said second clock signal is for clocking the computer system when said DMA mode is not executed, and said first clock signal is used to clock the system when said DMA mode is being executed.
A method for operating a computer system having a direct memory access (DMA) mode, comprising:
- generating a first clock signal;
- generating a second clock signal based on said first clock signal;
- outputting said second clock signal to a central processing unit (CPU) when said DMA mode is not executed;
- and
- stopping supplying said second clock signal to said CPU when said DMA mode is executed,
- wherein said second clock signal is for clocking the computer system when said DMA mode is not executed and said first clock signal is for clocking the system in said DMA mode.
Dependencies are inferred from the claim text.