System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver
An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.
Drawings
Claims24
An asynchronous serial port, comprising:
an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having at least 9 data bits;
and
a plurality of registers including a receive data register for storing the at least 9 data bits of the frame, wherein the receive data register further stores status bits indicating the status of the asynchronous serial receiver corresponding to the at least 9 data bits.
An asynchronous serial port, comprising:
an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having a plurality of data bits;
and
a plurality of registers including a receive data register for storing both the plurality of data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the received frame.
A microcontroller implemented as a single monolithic integrated circuit, comprising:
an execution unit for executing instructions;
and
an asynchronous serial port comprising:
an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having a plurality of data bits;
and
a plurality of registers including a receive data register for holding the plurality of data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the frame, the receive data register readable by a single read operation.
3 more elements
A microcontroller implemented as a single monolithic integrated circuit, comprising:
an execution unit for executing instructions;
and
an asynchronous serial port comprising:
an asynchronous serial receiver configurable for receiving a frame over a serial bus, the frame having at least 9 data bits;
and
a plurality of registers including a receive data register for holding the at least 9 data bits and status bits indicating the status of the asynchronous serial receiver corresponding to the frame, the receive data register readable by a single read operation.
3 more elements
A method of receiving high speed asynchronous data in a microcontroller that includes a DMA unit, an asynchronous serial port, and an execution unit, the method comprising the steps of:
receiving a frame of asynchronous serial data by the asynchronous serial port;
determining status conditions indicating the status of the
asynchronous serial port corresponding to the received frame;
performing a DMA transfer by the DMA unit receiving a receive data register containing the data bits of the received frame and status bits corresponding to the status conditions from the asynchronous serial port;
and
storing the read data item in a memory.
3 more elements
The method of claim 20, wherein the steps of claim 21 are repeated for a plurality of data items.
A microcontroller comprising:
means for receiving a frame of asynchronous serial data;
means for determining status conditions indicating the status of the receiving means corresponding to the received frame;
and means for transferring data bits and corresponding status bits reflecting the status condition from the means for receiving and the means for determining to a memory.
29 Aug 2017Estimated · howhide20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.
#The apparatus and method according to the invention pertains to microcontrollers, and more specifically, to a microcontroller providing high asynchronous serial port data rates using direct memory access.
#A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
#FIG. 1 is a block diagram of a typical microcontroller in which the techniques according to the invention can be implemented;
#FIG. 1A is a diagram of a data frame used in asynchronous serial communications;
Detailed description5,394 words
#Turning to FIG. 1, shown is a block diagram of a typical microcontroller M implemented according to the invention. Such a microcontroller is preferably implemented on a single monolithic integrated circuit. The microcontroller M preferably includes an internal bus 100 coupling a variety of functional units and registers used to control and monitor those units. These include a clock and power management unit 102 with corresponding clock/power registers 104, an interrupt control unit 106 with corresponding interrupt registers 108, a timer control unit 110 with corresponding timer registers 112, a direct memory access (DMA) unit 114 with corresponding DMA registers 116, a bus interface unit 118 with corresponding bus interface registers 120, an execution unit 124 which is essentially a microprocessor core, a chip select unit 126 with corresponding chip select registers 128, a programmable input/output (PIO) unit 132 with corresponding PIO registers 134, an asynchronous serial port 136 with corresponding asynchronous register 138, and a synchronous serial port 140 with corresponding synchronous registers 142. The clock and power management unit 102 includes external pads connected to a crystal 144, which provides the timing not only for the execution unit 124, but also for generating the serial clock in the asynchronous serial port 136.
#The block diagram of the microcontroller M is typical of microcontrollers, and could be for example, the Am186EM microcontroller by Advanced Micro Devices, Inc., of Sunnyvale, Calif. The techniques and circuitry according to the invention, however, could be applied to a wide variety of microcontrollers. Further, the term "microcontroller" has differing definitions in industry. Some companies refer to a processor core with additional features (such as I/O) as a "microprocessor" if it has no onboard memory, and digital signal processors (DSPs) are now used for both special and general purpose controller functions. So as here used, the term "microcontroller" covers all of the products, and generally means an execution unit with added functionality all implemented on a single monolithic integrated circuit.
#In many cases, a microcontroller containing an asynchronous serial port is configured to begin receiving asynchronous data via the asynchronous serial port 136. It will be recognized that the execution unit 124 of the microcontroller M executes instructions of software programs. The microcontroller M can be configured to cause an interrupt from the asynchronous serial port 136 when an asynchronous device sends data to the microcontroller M. That interrupt is then interpreted by the interrupt control unit 106 on the internal bus 100. Upon receiving an interrupt, the execution unit 124 stops program execution, saves the contents of certain critical registers (i.e., saves its internal state), and begins executing instructions of an appropriate interrupt service routine (such as an interrupt handler) associated with the asynchronous serial port 136. When execution of the interrupt service routine is completed, the execution unit 124 restores the saved contents of the critical registers (i.e., restores the internal state) and resumes execution of the interrupted program at the point where the interruption occurred.