System and method for I/O access mode selection

Adapter apparatus operable selectively in I/O mode or memory mapped mode, the apparatus including a register set, a memory, I/O logic, memory logic, and an option select register for selectively enabling said I/O logic or said memory logic, the improvement comprising:

• an I/O mode code routine for executing I/O mode functions;
• a memory mapped code routine for executing memory mode functions;
• a generic adapter access code routine for mapping a set of global data objects to said I/O mode functions and said memory mode functions;
• a mode switch routine for optimizing performance of said adapter apparatus by selectively statically and dynamically enabling mapping of said of global data objects to one of said I/O mode functions and said memory mode functions and said option select register to enable the corresponding I/O logic or memory logic;
• and
• other device driver code routine for issuing calls to said global data objects.

A memory device for storing signals for controlling the operation of a computer channel adapter according to the method for optimizing adapter performance characteristics comprising the steps of

• initializing a generic adapter access routine with global data objects as pointers to corresponding sets of alternative adapter functions;
• initializing said channel adapter to function in a first mode and to map said pointers to a corresponding current set of adapter functions;
• executing other device driver code calls to global data objects by reference to said current set of adapter functions;
• responsive to a request to switch modes to optimize adapter performance, dynamically switching said channel adapter to a second mode and remapping said pointers to a corresponding second set of adapter functions.

A memory device for storing signals for structuring a digital computer to interface an adapter, said adapter including a register set, a memory, I/O logic, memory logic, and an option select register for selectively enabling said I/O logic or said memory logic, said computer comprising:

• an I/O mode code routine for executing I/O mode functions;
• a memory mapped code routine for executing memory mode functions;
• a generic adapter access code routine for mapping a set of global data objects to said I/O mode functions and said memory mode functions;
• a mode switch routine for optimizing performance of said adapter by selectively statically and dynamically enabling mapping of said of global data objects to one of said I/O mode functions and said memory mode functions and said option select register to enable the corresponding I/O logic or memory logic;
• and
• a device driver code routine for issuing calls to said global data objects for accessing said adapter.