Two-bit booth multiplier with reduced data path width

A multiplier circuit for performing multiplication through manipulation of a plurality of signals, the plurality of signals including at least a multiplier, a multiplicand and a partial product the multiplier circuit comprising:

• an adder having a first input terminal, a second input terminal, and an output terminal;
• a plurality of shift registers including:
• a multiplicand register having an output terminal coupled to the first input terminal of the adder;
• a temporary shift register having an output terminal coupled to the second input terminal of the adder and having an input terminal coupled to the output terminal of the adder;
• and
• a multiplier shift register having an input terminal coupled to receive least significant bits of the partial product from the output terminal of the adder, and the input terminal of the multiplier shift register coupled to receive a shifted version the multiplier, the multiplier shift register having an output terminal;
• a shift logic coupled between the adder and the plurality of shift registers;
• and
• a Booth logic circuit having an input terminal coupled to the output terminal of the multiplier shift register and having an output terminal coupled to the shift logic, the Booth logic circuit controlling a two-bit Booth multiplier operation designating multiplicand partial product operations including +0 and .+-.x partial product operations and implementing .+-.2x partial product operations using the .+-.x multiplicand partial product operations while shifting data from the temporary shift register one bit right on application to the adder.

A method of multiplying integer numbers in a processor having an adder, a multiplicand register, a temporary register, a multiplier shift register, and a Booth logic circuit, the method comprising:

• receiving least significant bits of a partial product in the multiplier shift register from the adder:
• receiving a shifted version of a multiplier in the multiplier shift register;
• testing two bits of data in the multiplier shift register and the most significant bit of a previous two-bit group to determine whether a partial product value of +0, .+-.x, or .+-.2x is designated;
• if a partial product value of +0 is designated, adding a zero data to a temporary data in the temporary register and replacing the temporary register with the sum right shifted by two bits;
• if a partial product value of +x is designated, adding a multiplicand data in the multiplicand register to the temporary data in the temporary register and replacing the temporary register with the sum right shifted by two bits;
• if a partial product value of -x is designated, complementing the multiplicand data in the multiplicand register, incrementing the complemented multiplicand data by 1, and adding the complemented multiplicand data to the temporary data in the temporary register and replacing the temporary register with the sum right shifted by two bits;
• if a partial product value of +2x is designated, shifting the temporary data in the temporary register right one bit and adding the multiplicand data in the multiplicand register to the shifted temporary data in the temporary register and replacing the temporary register with the sum right shifted by one bit;
• if a partial product value of -2x is designated, shifting the temporary data in the temporary register right one bit, complementing the multiplicand data in the multiplicand register, incrementing the complemented multiplicand data by 1, and adding the complemented multiplicand data to the shifted temporary data in the temporary register and replacing the temporary register with the sum right shifted by one bit;
• and
• shifting data in the multiplier shift register, the multiplicand register and the temporary register two bits right, the low-order bits of the temporary register being moved into the high-order bits of the multiplier shift register and the low-order bits of the multiplier being discarded.