Efficient floating point normalization mechanism

An apparatus for normalizing a floating point result in a processor, comprising:

• receiving means for receiving a plurality of operand mantissas in an adder;
• adder means for generating a result mantissa in said adder equivalent to a sum of said plurality of operand mantissas;
• first signal means for generating a shift control signal in said processor for shifting said result mantissa by an amount corresponding to a minimum position for a leading one in said result mantissa;
• exponent calculator means for adjusting an operand exponent to generate an intermediate result exponent corresponding to shifting said result mantissa by said amount corresponding to said minimum position;
• first shifting means for partially shifting said result mantissa in response to said shift control signal;
• detector means for detecting a position of said leading one in said partially shifted result mantissa;
• and
• second shifting means and second signal means, responsive to said detection of said position of said leading one, for shifting said partially shifted result mantissa and for generating an exponent carry-in signal to adjust said intermediate exponent, wherein a floating point result is efficiently normalized.

A normalizing mechanism in a processor, comprising:

• a main adder receiving a plurality of operand mantissas and generating a result mantissa equivalent to a sum of said plurality of operand mantissas;
• a leading zero anticipator generating a shift control signal corresponding to a predicted minimum position for a leading one in said result mantissa;
• an exponent calculator generating, from an operand exponent, an intermediate result exponent corresponding to shifting said result mantissa to said predicted minimum position;
• first and second shifting multiplexers partially shifting said result mantissa in response to said shift control signal to generate a partially shifted result mantissa;
• a leading zero detector detecting a position of said leading one in said partially shifted result mantissa and generating an exponent carry-in signal to adjust said intermediate exponent;
• and
• a third shifting multiplexer, responsive to said detection of said position of said leading one, shifting said partially shifted result mantissa, wherein said normalizing mechanism efficiently normalizes a floating point result.

A processor having an efficient normalization mechanism, comprising:

• a multiplier receiving a plurality of operand mantissas and reducing a multiplication operation between said plurality of operand mantissas to a sum of two intermediate operands;
• an exponent calculator receiving a plurality of operand exponents and calculating an intermediate exponent, said exponent calculator operating in parallel with said multiplier;
• a main adder receiving said two intermediate operands and calculating an intermediate mantissa equalling a sum of said two intermediate operands;
• a leading zero anticipator receiving said intermediate exponent and predicting a position of a leading one in a result to an error of one bit position in one direction and computing a normalize adjust equalling a minimum predicted shift, said leading zero anticipator operating in parallel with said main adder;
• a normalizer receiving said intermediate mantissa and said normalize adjust and shifting said intermediate mantissa by an amount equalling said minimum predicted shift to generate a shifted mantissa;
• an exponent adder receiving said normalize adjust and computing an adjusted exponent corresponding to said minimum predicted shift;
• and
• a leading zero detector receiving said shifted mantissa and determining a position of a leading one in said shifted mantissa, said leading zero detector asserting a carry-in to said exponent adder to generate a result exponent and signaling said normalizer to forward said shifted mantissa as a result mantissa if said minimum predicted shift equals a required shift, wherein a normalized floating point result is efficiently calculated.