Digital data comparator and microprocessor
AssigneeKabushiki Kaisha Toshiba
InventorMikio Shiraishi
Life of this patent
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Abstract
The present invention provides a digital data comparator having a first selective data inverting circuit inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive, a first adding circuit coupled to an output of the first selective data inverting circuit, adding one to the least significant bit when the sign of the first input data is negative, or outputting the first input data when the sign is positive, a second selective data inverting circuit inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the sign is negative, and a second adding circuit adding an output of the first adding circuit and an output of the second selective data inverting circuit.
Claims26
A digital data comparator comprising:
- a first selective data inverting means inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive;
- a first adding means coupled to an output or the first selective data inverting means, adding one to the least significant bit when the sign of the first input data is negative, or outputting the first input data when the sign is positive;
- a second selective data inverting means inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the sign is negative;
- and
- a second adding means adding an output of the first adding means and an output of the second selective data inverting means.
A digital data comparator comprising:
- a first selective data inverting means inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive;
- a second selective data inverting means inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the sign is negative;
- a first adding means coupled to an output of the second selective data inverting means, adding one to the least significant bit when the sign of the second input data is positive, or outputting the second input data when the sign is negative;
- and
- a second adding means adding an output of the first adding means and an output of the first selective data inverting means.
A microprocessor comprising:
- a first selective data inverting means inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive;
- a first adding means coupled to an output of the first selective data inverting means, adding one to the least significant bit when the sign of the first input data is negative, or outputting the first input data when the sign is negative;
- a second selective data inverting means inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the sign is negative;
- and
- an arithmetic logic unit having an adding means including a carry signal input terminal, adding an output of the first adding means and an output of the second selective data inverting means.
A microprocessor comprising:
- a first selective data inverting means inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the code is positive;
- a second selective data inverting means inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the code is negative;
- a first adding means coupled to an output of the second selective data inverting means, adding one to the least significant bit when the sign of the second input data is positive, or outputting the second input data when the sign is negative;
- and
- an arithmetic logic unit having an adding means including a carry signal input terminal, adding an output of the first adding means and an output of the first selective data inverting means.
Dependencies are inferred from the claim text.