Built in self repair for DRAMs using on-chip temperature sensing and heating

A method for on-chip testing and repairing of memories in a system that contains a heating element, a test circuit, a repair circuit, a memory array, and a plurality of redundant memory locations within the memory array, the method comprising the steps of:

• heating the memory array to a predetermined operating temperature;
• testing the memory array;
• determining an original address of a faulty location in the memory array;
• and
• repairing the faulty location by using the repair circuit to redirect the original address to an address of a redundant memory location.

An on-chip system for detecting and repairing data retention faults under normal operating conditions, wherein the system comprises:

• a memory array including a plurality of memory cells;
• a plurality of redundant memory cells coupled to the memory array for replacing faulty memory cells;
• a heating element coupled to the memory array for heating the memory array to a predetermined operating temperature;
• a testing unit coupled to the memory array for testing the memory array and determining an original address of a faulty memory cell;
• and
• a repair module coupled to the memory array and the testing unit for repairing the faulty memory cell with a redundant memory cell by redirecting the original address to an address of the redundant memory cell.

An on-chip system for detecting and repairing data retention faults, wherein the system comprises:

• a memory array including a plurality of memory cells;
• a plurality of redundant memory cells coupled to the memory array for replacing faulty memory cells;
• a heating element coupled to the memory array for heating the memory array;
• a testing unit coupled to the memory array for testing the memory array and determining an original address of a faulty memory cell;
• and
• a repair module coupled to the memory array and the testing unit for repairing the faulty memory cell with a redundant memory cell by redirecting the original address to an address of the redundant memory cell.