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US 5,953,241 AGranted
Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
AssigneeMicrounity Engeering Systems, Inc.
InventorsCraig C. Hansen, Henry Massalin
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Abstract
A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.
Claims7
A multiplier processing system for performing a group-multiply-and-sum instruction, said system comprising:
- means for partitioning each of a plurality of operands into a plurality of symbols, said operands having a first defined bit width and said symbols having a a second defined bit width, said second defined bit width of said symbols being dynamically variable;
- means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product;
- and
- means for adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said first defined bit width of said operands without a reduction in the accuracy of said result.
1 more element
A multiplier processing system for performing a group-multiply-sum-and-add instruction, said system comprising:
- means for partitioning each of a plurality of operands into a plurality of symbols, said operands having a first defined bit width and said symbols having a second defined bit width, said second defined bit width of said symbols being dynamically variable;
- means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product;
- and
- means for adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said first defined bit width of said operands without a reduction in the accuracy of said result.
1 more element
Dependencies are inferred from the claim text.