Anti-wafer breakage detection system
AssigneeCypress Semiconductor Corporation
InventorDanial D. Harvey
Life of this patent
Estimating the term…
Abstract
A circuit configured to generate an error signal that may be used to disable a loading mechanism (such as a loading mechanism in a wafer sorter). The circuit comprises a wafer sense circuit configured to generate a first pulse in response to a wafer passing a detection point, a pulse generator circuit configured to generate (i) a second pulse in response to a transition (e.g., a positive transition) of the first pulse and (ii) a third pulse in response to a transition (e.g., a negative transition) of the first pulse. An error detection block may be configured to generate an error signal in response to (i) the first pulse, (ii) the second pulse and (iii) the third pulse.
Claims17
A circuit comprising:
- a first circuit configured to generate a first pulse in response to a wafer passing a detection point;
- a second circuit configured to generate (i) a second pulse representing a first time window in response to a first transition of the first pulse and (ii) a third pulse representing a second time window in response to a second transition of the first pulse;
- and
- a third circuit configured to generate an error signal in response to (i) said first pulse, (ii) said second pulse and (iii) said third pulse, wherein said error signal has an active state corresponding to said wafer remaining in or at said detection point for a time greater than said first time window or is in or at said detection point during said second time window, said active error signal automatically disabling a wafer loading mechanism or transport mechanism or device.
An apparatus comprising:
- means for generating a first pulse in response to a wafer passing a detection point;
- means for generating (i) a second pulse representing a first time window in response to a first transition of the first pulse and (ii) a third pulse representing a second time window in response to a second transition of the first pulse;
- and
- means for generating an error signal in response to (i) said first pulse, (ii) said second pulse and (iii) said third pulse, wherein said error signal has an active state corresponding to said wafer remaining in or at said detection point for a time greater than said first time window or is in or at said detection point during said second time window, said active error signal automatically disabling a wafer loading mechanism or transport mechanism or device.
A method for disabling a loading mechanism comprising the steps of:
- generating a first pulse in response to a wafer passing a detection point;
- generating (i) a second pulse representing a first time window in response to a first transition of the first pulse and (ii) a third pulse representing a second time window in response to a second transition of the first pulse;
- and
- generating an error signal in response to (i) said first pulse, (ii) said second pulse and (iii) said third pulse, wherein said error signal has an active state corresponding to said wafer remaining in or at said detection point for a time greater than said first time window or is in or at said detection point during said second time window, said active error signal automatically disabling a wafer loading mechanism or transport mechanism or device.
Dependencies are inferred from the claim text.