Multiprocessor system and its control method

A control method of a multiprocessor system, comprising:

• a resetting step of resetting each of shared sections including a plurality of processors connected through a shared bus and a read only memory unit in which common program information that is operated by said plurality of processors has been stored at the time of system activation;
• a processor authority allocating step of judging the processors effectively connected to the system after the resetting in said resetting step, allocating a master authority to one of said plurality of effective processors, setting said one of the effective processors to a master processor, allocating a slave authority to all of the other remaining processors, and setting said remaining processors to slave processors;
• an initialization diagnosing step of sequentially executing peculiar initialization diagnosing processes in accordance with the order of said master processor and said slave processors;
• and
• a distributing processing step of distributing a job to said plurality of processors and executing the job at the stare when said initialization diagnosing process is normally finished,
• wherein said processor authority allocating step includes:
• a wake-up step of setting a wake-up bit of a wake-up register provided for each of said processors after completion of the resetting of each of said processors,
• an effective processor setting step of using the processor in which said wake-up bit was set in said wake-up step as a processor that is effective in the system and setting the corresponding bit of the processor effective register provided for said processor,
• a system connection processor detecting step of detecting a physical connection of the processors to said shared bus and setting a corresponding bit of a processor connection register provided for the shared section which can be referenced by all of said processors,
• an authority recognizing step of recognizing a self processor ID number from ID numbers which have been stored in a processor number register provided for each of said processors, comparing said recognized ID number with the processor ID numbers of the other processors shown by the effective register obtained in said effective processor setting step, recognizing that the self processor is a master processor when said self processor ID number is minimum or maximum, and recognizing that the self processor is a slave processor when said self processor ID number is other than the minimum or maximum ID number,
• an initialization diagnosing step of sequentially executing peculiar initialization diagnosing processes in accordance with the order of said master processor and said slave processor, and
• a distributing processing step of distributing a job to said plurality of processors and executing said job at the stage when said initialization diagnosing step is normally finished,
• wherein said initialization diagnosing step comprises:
• a master monitoring step of monitoring by each of said slave processors whether the initializing diagnosis of said master processor has normally been finished or not;
• and
• a degenerating processing step which is constructed in a rule such that in the case where either one of said slave processors detects an abnormality of said master processor in said master monitoring step, said master processor is disconnected from the system and is degenerated, a new master processor and new slave processors are allocated to the other remaining processors as targets by said processor authority allocating step, and processes are again executed after that, and
• wherein said master monitoring step comprises:
• a threshold time setting step of setting a threshold time (Ti) for master monitoring which becomes short as a priority is high in accordance with a priority of the master authority allocation that is determined by a processor number (i) into each slave processor;
• a counting step of getting a synchronization when idle states of all of said processors are recognized by referring to a processor arrival register which is provided in said shared section and sets an operating state and the idle state of each processor, and starting a time counting of a master monitoring time (T) based on a start of the initialization diagnosing process to monitor an initializing diagnosis of said master processor in each of said slave processors;
• and
• a master abnormality judging step which is constructed in a rule such that the presence or absence of the end of the initializing diagnosis by said master processor is monitored during the time counting in said counting step, in the case where the end of the initializing diagnosis is recognized when the counting time (T) lies within said threshold time (Ti), it is judged that the master processor is normal, the processing routine advances to the initialization diagnosing process of a next said slave processor, and in the case where the end of the initializing diagnosis cannot be recognized even when the counting time (T) reaches the shortest threshold time (Ti), it is judged that said master processor is abnormal, the slave processor in which the shortest threshold time has been set is set to a new master processor, and the processing routine advances to said degenerating process.