Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes

A method of operating a computer system having a type of configuration and comprising a single integrated circuit microprocessor, wherein the single integrated circuit microprocessor includes a read only original code memory not directly accessible externally to the single integrated circuit microprocessor and a patch memory table, operates in response to original codes stored in corresponding addresses in the read only original code memory and comprises an instruction set, the method comprising the steps of:

• determining the type of the configuration;
• in response to the type of the configuration, selecting a set of patch codes from a plurality of sets of patch codes;
• evaluating a key within the single integrated circuit microprocessor;
• and
• issuing a patch request instruction from the instruction set to the single integrated circuit microprocessor;
• in response to issuing the patch request instruction
• storing the selected set of patch codes to a memory space accessible by the microprocessor in response to the key satisfying at least a first criterion;
• storing in the patch table memory an indication of each address in the read only original code memory storing a corresponding original code to be replaced by one of the selected set of patch codes in response to the key satisfying at least a first criterion;
• setting a lock indicator, wherein the locked indicator in a locked stated represents that the selected set of patch codes are stored to the memory space;
• detecting a request within the single integrated circuit microprocessor for an original code from the read only original code memory;
• determining from the indication of each address stored in the patch table memory whether a requested original code is to be replaced by a patch code;
• operating in response to the requested original code upon determination that the requested original code is not to be replaced by a patch code;
• and
• substituting a corresponding patch code from the memory space for the requested original code and operating in response to the substituted patch code upon determination that the requested original code is to be replaced by a patch code.

A computer system having a type of configuration and comprising:

• an input device;
• an output device;
• a single integrated circuit microprocessor, said single integrated circuit microprocessor including a read only original code memory not directly accessible externally to the single integrated circuit microprocessor and a patch code table memory, wherein the microprocessor operates in response to original codes recalled from corresponding addresses in said read only original code memory and comprises an instruction set;
• a memory space accessible by said single integrated circuit microprocessor;
• a computer-readable memory configured so that, when read and used by the computer system, the computer system is directed by a plurality of operations comprising:
• determining the type of the configuration;
• in response to the type of the configuration, selecting a set of patch codes from a plurality of sets of patch codes;
• issuing a patch request instruction from the instruction set;
• and
• in response to issuing a patch request instruction
• storing the selected set of patch codes to a memory space,
• storing in the patch table memory an indication of each address in the read only original code memory storing a corresponding original code to be replaced by one of the selected set of patch codes;
• said single integrated circuit microprocessor further including means for generating a code address of a next original code, said code address supplied to said read only original code memory for recall of said next original code and to said patch table memory;
• and
• said single integrated circuit microprocessor further including a multiplexer having a first input receiving original codes recalled from said read only original code memory, a second input receiving patch codes recalled from said memory space accessible by said single integrated circuit microprocessor, a control input connected to said patch code table receiving said indication of whether said corresponding original code is to be replaced by one of the selected set of patch codes and an output coupled to said first input if said indication stored in said patch code table memory indicates that the requested original code is not to be replaced by a patch code and coupled to said second input if said indication stored in said patch code table indicates that the requested original code is to be replaced by a patch code.