Programmable interconnect junction
AssigneeAltera Corporation
InventorsChristopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
Life of this patent
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Abstract
A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
Claims48
A programmable switch comprising:
- a first interconnect line;
- a second interconnect line;
- an interconnect element for programmably coupling the first interconnect line to the second interconnect line;
- a floating gate, programmably controlling the interconnect element;
- and
- a margin device coupled to permit evaluation of a programming margin of the floating gate, wherein the interconnect element is a first transistor and the floating gate is a gate of the first transistor.
A configurable interconnect junction comprising:
- a memory cell comprising:
- a floating gate;
- a tunnel diode;
- a tunnel dielectric coupled to transfer electrons between the tunnel diode and the floating gate;
- and
- a margin device coupled to permit evaluation of a programming margin of the memory cell;
- and
- a switch coupled between a first conductor and a second conductor, wherein the floating gate of the memory cell is a control node of the switch.
A semiconductor structure comprising:
- a floating gate;
- a row-line conductor;
- a first active region comprising:
- a switch transistor formed by the floating gate, wherein the floating gate programmably couple a first node of the switch transistor and a second node of the switch transistor;
- and
- a second active region comprising:
- a read transistor formed by the row-line conductor;
- and
- a program transistor formed by the floating gate and serially coupled to the read transistor.
A semiconductor structure comprising:
- a floating gate;
- a row-line conductor;
- a first active region comprising:
- a switch transistor controlled by the floating gate to programmably couple a first node of the switch transistor and a second node of the switch transistor;
- and
- a second active region comprising:
- a read transistor, having a control node coupled to the row-line conductor;
- and
- a program transistor, serially coupled with the read transistor and controlled by the floating gate;
- a third active region comprising:
- a tunnel diode, beneath a tunnel dielectric and the floating gate, wherein charge is transferred between the tunnel diode and the floating gate through the tunnel dielectric;
- and
- a fourth active region comprising:
- a control gate capacitor coupled to the floating gate.
A programmable switch matrix comprising:
- a source line;
- a drain line;
- a read transistor;
- a program transistor having a control gate and programmable gate, whereby the read transistor and program transistor are serially coupled between the source line and the drain line;
- and
- a first programmable switch controlled by the programmable gate for coupling a first interconnect conductor to a second interconnect conductor.
A programmable switch comprising:
- a first interconnect line;
- a second interconnect line;
- an interconnect element for programmably coupling the first interconnect line to the second interconnect line, wherein the interconnect element has a doping profile comprising:
- a first portion having a first doping concentration;
- and
- a second portion, below the first portion, having a second doping concentration, wherein the first doping concentration is less than the second doping concentration, whereby the doping profile increases longevity of the programmable switch;
- a floating gate, programmably controlling the interconnect element;
- and
- a margin device coupled to permit evaluation of a programming margin of the floating gate.
A programmable switch comprising:
- a first interconnect line;
- a second interconnect line;
- an interconnect element for programmably coupling the first interconnect line to the second interconnect line;
- a floating gate, programmably controlling the interconnect element;
- a margin device coupled to permit evaluation of a programming margin of the floating gate;
- and
- a tunnel diode coupled to transfer electrons to and from the floating gate.
A programmable switch comprising:
- a first interconnect line;
- a second interconnect line;
- an interconnect element for programmably coupling the first interconnect line to the second interconnect line;
- a floating gate, programmably controlling the interconnect element;
- a margin device coupled to permit evaluation of a programming margin of the floating gate;
- a tunnel diode coupled to transfer electrons to and from the floating gate;
- and
- a write transistor coupled to pass a voltage to the tunnel diode.
A programmable switch comprising:
- a first interconnect line;
- a second interconnect line;
- an interconnect element for programmably coupling the first interconnect line to the second interconnect line;
- a floating gate, programmably controlling the interconnect element;
- and
- a margin device coupled to permit evaluation of a programming margin of the floating gate, wherein to program the programmable switch, a program voltage is coupled to a control gate coupled to the interconnect element and the margin device, and an assist voltage is coupled to the first interconnect line.
Dependencies are inferred from the claim text.