Vias and method for making the same in organic board and chip carriers

A method of making multiple vias having generally parallel axes in a printed circuit board or chip carrier comprising the steps of:

• (a) providing a primary through-hole in said circuit board or chip carrier, said through-hole extending from a top to a bottom surface of said circuit board or chip carrier;
• (b) metallizing said primary through-hole to provide a conductive path from said top surface to said bottom surface of said circuit board or chip carrier;
• (c) filling or coating said metallized through-hole with a dielectric material and covering said top and bottom surfaces with a first dielectric layer;
• (d) forming at least two secondary through-holes having longitudinal axes parallel to each other and parallel to a longitudinal axis of said primary through-hole through said dielectric in said primary through-hole and through said first dielectric layer on said top and bottom surfaces, said secondary through-holes being spaced apart from and not in contact with said metallization on said primary through-hole;
• (e) metallizing said secondary through-holes to provide conductive paths between said top and bottom surfaces covered with said first dielectric layer;
• (f) filling or coating said metallized secondary through-holes with a dielectric material and applying a second dielectric layer to cover said top and bottom surfaces covered with said first dielectric layer and said secondary through holes;
• and
• (g) removing portions of one of said top and bottom layers of said dielectric covering one of said top and bottom surface of said circuit board or chip carrier to permit making independent electrical contacts with said primary and said secondary metallized through-holes, respectively.