US 5,946,244 A · Delay-locked loop with binary-coupled capacitor

Abstract

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Claims21

Dependent claims

A delay-locked loop adapted to produce a delayed output signal in response to an input signal at a selected frequency, comprising:

a variable delay circuit having an input terminal, an output terminal, and a control input terminal, the delay circuit including a capacitor bank having a variable capacitance corresponding to a digital control signal adapted to be applied to the control input terminal, the delay circuit being operative to provide the delayed output signal at the output terminal in response to the input signal, the delayed output signal being delayed relative to the input signal by a delay corresponding to the capacitance;
and
a comparing circuit having a first input coupled to the input terminal, a second input coupled to the output terminal, and a control output coupled to the control input terminal, the comparing circuit being configured to provide the digital control signal at the control output in response to the relative phases of the input signal and the delayed output signal.

A memory device responsive to an input clock signal, comprising:

a command input terminal;
a clock input terminal;
a memory array;
a buffer amplifier having an amplifier input coupled to the clock input terminal and a buffer output, the buffer amplifier being responsive to the input clock signal at the amplifier input to produce a buffered clock signal having a phase shift relative to the input clock signal;
a delay-locked loop adapted to produce a plurality of phase shifted signals in response to the buffered clock signal, the delay-locked loop comprising:
a variable delay circuit having an input terminal coupled to the buffer output, an output terminal, and a control input terminal, the delay circuit including a capacitor bank having a variable capacitance corresponding to a digital control signal adapted to be applied to the control input terminal the delay circuit being operative to provide the delayed output signal at the output terminal in response to the buffered clock signal, the delayed output signal being delayed relative to the buffered clock signal by a delay corresponding to the capacitance;
and
a comparing circuit having a first input coupled to the input terminal, a second input coupled to the output terminal, and a control output coupled to the control input terminal, the comparing circuit being configured to provide the digital control signal at the control output in response to the relative phases of the buffered clock signal and the delayed output signal;
and
a control circuit having a command input coupled to the command input terminal, a clock input coupled to the output terminal of the delay-locked loop, and a control output coupled to the memory array, the control circuit being configured to control transfers of data into and out of the memory array in response to the delayed output signal.

7 more elements

Dependencies are inferred from the claim text.

Delay-locked loop with binary-coupled capacitor

Life of this patent

Delay-locked loop with binary-coupled capacitor

Life of this patent

Abstract

Claims21