US 5,945,855 AGranted

High speed phase lock loop having high precision charge pump with error cancellation

AssigneeAdaptec, Inc.

InventorAfshin D. Momtaz

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Abstract

A high precision charge pump used in a phase-lock loop incorporating a type-IV phase/frequency detector is designed and constructed to substantially eliminate the effects of ringing and glitch errors on the charge pump output current as averaged over a pump-up and pump-down cycle by the type-IV phase/frequency detector. The high precision charge pump is constructed exclusively of transistors of a single polarity (N-channels) that are so matched as to each have the same current characteristics. The current pulse length, absolute magnitude, and waveform envelopes of the charge pumps source and sink currents are defined by matched transistors. When the type-IV phase/frequency detector is operating in quasi flywheel mode, and no phase comparisons are being made, the charge pump's source current is equal to the sink current in all significant respects such that no incremental, residual charge is left on a loop capacitor following the conclusion of a sequential pump-up and pump-down sequence.

Claims9

Dependent claims

In a PLL of the type including a type-IV phase detector in which pump-up and pump-down signals are provided to a charge pump on a continuous basis irrespective of the occurrence of a phase comparison, the charge pump sourcing and sinking a characteristic current in operative response to the pump-up and pump-down signals, the charge pump comprising:

a first, outer, current conduction path including first and second transistors connected together at a first common drain node and to a first current source configured to conduct a characteristic current, the first common drain node defining a charge pump output, the first and second transistors each having a source node and connected to respective second and third current sources each configured to conduct said characteristic current;
a second, inner, current conduction path including third and fourth transistors connected together at a second common drain node and each having a source node connected to a respective one of said second and third current sources;
and
voltage follower means coupled between the first and second common drain nodes of the inner and outer conduction paths for maintaining the drain potential of the inner path at substantially the same value as the drain potential of the outer path.

1 more element

Dependencies are inferred from the claim text.