US 5,945,847 A · Distributed amplifier logic designs

Abstract

A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C.sub.gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.

Claims38

Dependent claims

A high speed logic module comprising

a pair of logic devices, each device including a gate terminal, a drain terminal and a source terminal, the source terminals being coupled to receive a predetermined signal;
a differential input comprising a pair of transmission lines, each input transmission line coupled to a separate one of the gate terminals of said pair of logic devices;
a differential output comprising a pair of transmission lines, each output transmission line coupled to a separate one of the drain terminals of said pair of logic devices;
and
a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between said drain terminal of a first logic device of said pair of logic devices and said gate terminal of a second logic device of said pair of logic devices, and a second neutralizing reactive element coupled between said drain terminal of said second logic device and said gate terminal of said first logic device.

2 more elements

A distributed exclusive-OR logic circuit comprising a plurality of differential exclusive-OR logic modules, said exclusive-OR logic circuit including

a first differential input comprising a first pair of input transmission lines;
a second differential input comprising a second pair of input transmission lines;
a differential output comprising a pair of output transmission lines;
and
a plurality of exclusive-OR logic modules, each exclusive -OR logic module comprising
a first pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines;
a second pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines, said second pair of logic devices disposed in a cross-coupled relationship with said first pair of logic devices in a manner whereby said second pair of logic devices provides neutralization to the intrinsic capacitance associated with said first pair of logic devices;
a third pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said second pair of input transmission lines and said pair of output transmission lines;
and
a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between the drain terminal of a first logic device and gate terminals of a second logic device of said third pair of logic devices and a second neutralizing reactive element coupled between the drain terminal of said second device and the gate terminal of said first device of said third pair of logic devices.

7 more elements

A distributed latch circuit comprising

a differential signal input comprising a pair of signal input transmission lines;
a differential clock input comprising a pair of clock input transmission lines;
a differential output comprising a pair of output transmission lines;
and
a plurality of latch logic circuit modules, each latch logic circuit module comprising
a first pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said first pair of logic devices coupled to separate ones of said pair of signal input transmission lines and the drain terminals of said first pair of logic devices coupled to separate ones of said pair of output transmission lines;
a first pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said first pair of logic devices;
a second pair of logic devices, each including a gate terminal, a drain terminal, and a source terminal, the gate terminals of said second pair of logic devices being coupled to separate ones of said pair of output transmission lines and the drain terminals of said second pair of logic devices coupled, in an opposing arrangement, to said pair of output transmission lines such that the gate and drain terminals of each device are coupled to different output transmission lines;
a second pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said second pair of logic devices;
a third pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said third pair of logic devices being coupled to separate ones of said pair of clock input transmission lines, the source terminals being coupled together and applied to a power supply, the drain terminal of a first device of said third pair of logic devices being coupled to both source terminals of said first pair of logic devices and the drain terminal of a second device of said third pair of logic devices being coupled to both source terminals of said second pair of logic devices;
and
a third pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said third pair of logic devices.

9 more elements

An integrated circuit including a distributed exclusive-OR logic circuit comprising a plurality of differential exclusive-OR logic modules, said exclusive-OR logic circuit including

a first differential input comprising a first pair of input transmission lines;
a second differential input comprising a second pair of input transmission lines;
a differential output comprising a pair of output transmission lines;
and
a plurality of exclusive-OR logic modules, each exclusive-OR logic module comprising
a first pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines;
a second pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said first pair of input transmission lines and said pair of output transmission lines, said second pair of logic devices disposed in a cross-coupled relationship with said first pair of logic devices in a manner whereby said second pair of logic devices provides neutralization to the intrinsic capacitance associated with said first pair of logic devices;
a third pair of logic devices, each device including a drain terminal, a gate terminal and a source terminal, coupled between said second pair of input transmission lines and said pair of output transmission lines;
and
a pair of neutralizing reactive elements, a first neutralizing reactive element coupled between the drain terminal of a first logic device and gate terminals of a second logic device of said third pair of logic devices and a second neutralizing reactive element coupled between the drain terminal of said second device and the gate terminal of said first device of said third pair of logic devices.

7 more elements

An integrated circuit comprise a distributed latch circuit comprising

a differential signal input comprising a pair of signal input transmission lines;
a differential clock input comprising a pair of clock input transmission lines;
a differential output comprising a pair of output transmission lines;
and
a plurality of latch logic circuit modules, each latch logic circuit module comprising
a first pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said first pair of logic devices coupled to separate ones of said pair of signal input transmission lines and the drain terminals of said first pair of logic devices coupled to separate ones of said pair of output transmission lines;
a first pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said first pair of logic devices;
a second pair of logic devices, each including a gate terminal, a drain terminal, and a source terminal, the gate terminals of said second pair of logic devices being coupled to separate ones of said pair of output transmission lines and the drain terminals of said second pair of logic devices coupled, in an opposing arrangement, to said pair of output transmission lines such that the gate and drain terminals of each device are coupled to different output transmission lines;
a second pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said second pair of logic devices;
a third pair of logic devices, each including a gate terminal, a drain terminal and a source terminal, the gate terminals of said third pair of logic devices being coupled to separate ones of said pair of clock input transmission lines, the source terminals being coupled together and applied to a power supply, the drain terminal of a first device of said third pair of logic devices being coupled to both source terminals of said first pair of logic devices and the drain terminal of a second device of said third pair of logic devices being coupled to both source terminals of said second pair of logic devices;
and
a third pair of neutralizing reactive elements disposed in a cross-coupled arrangement between the drain and gate terminals of said third pair of logic devices.

9 more elements

Dependencies are inferred from the claim text.

Distributed amplifier logic designs

Life of this patent

Distributed amplifier logic designs

Life of this patent

Abstract

Claims38