Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

A method for testing a plurality of semiconductor chips disposed on a semiconductor wafer comprising the steps of:

• placing said semiconductor wafer comprising a plurality of integrated circuit terminals for testing said plurality of semiconductor chips so as to be retained by a retainer board;
• disposing a wiring board comprising a plurality of probe terminals and a wire which are electrically connected to each other and said retainer board retaining said semiconductor wafer, such that said plurality of probe terminals face said integrated circuit terminals, respectively, and further disposing a sealing member such that a hermetic space is formed by said retainer board, said wiring board and said sealing member are provided in the periphery of said hermetic space;
• depressurizing said hermetic space, to bring said probe terminals of said wiring board and said integrated circuit terminals of said semiconductor wafer into contact with each other;
• setting said wiring board, said retainer board and said sealing member while maintaining said hermetic space at a depressurized state, into a burn-in rack for testing;
• and testing said plurality of semiconductor chips by inputting a power-source voltage or a signal for testing to said integrated circuit terminals of said semiconductor wafer via said wire and said probe terminals of said wiring board.