US 5,944,840 A · Continuous monitor for interrupt latency in real time systems

Abstract

Apparatus and a method for monitoring the time for a computer to process a process associated with an interrupt asserted on a system bus. When the interrupt is asserted, a time stamp value and data associated with the interrupt are stored in one of a plurality of registers. The data associated with the interrupt include an identification of the type of interrupt, the bus, and a device asserting the interrupt. Whenever a time stamp value and associated data are stored in a register, a flag is set ON to indicate information is stored therein. The time stamp value and associated data are stored in an overflow register if every other register is in use. A latency value for the interrupt is determined from the difference between the time stamp value stored in a register and the time when processing of the interrupt process is complete. Interrupts that are asserted by various devices on a plurality of different buses can be monitored, and the latency values and associated data for each interrupt can be determined and stored. A report showing the latency times for the different interrupts can be produced. In addition, an alarm can be produced if the latency time for any interrupt exceeds a predetermined maximum value.

Claims30

Dependent claims

A method for determining an amount of time required for a computer to process an interrupt, comprising the steps of:

(a) determining when the interrupt is asserted, assertion of the interrupt causing the computer to subsequently initiate an interrupt service routine;
(b) storing a temporal value indicating a time when the interrupt is asserted;
(c) determining a current time when the computer has initiated the interrupt service routine;
and
(d) determining a latency value for the interrupt that corresponds to a difference between the temporal value that was stored and the current time, said latency value being employed as an indication of the amount of time required for the computer to initiate the interrupt service routine.

2 more elements

A system for determining an amount of time required for a computer to process an interrupt, comprising:

(a) a memory that stores a plurality of logical steps;
and
(b) an interrupt latency monitor coupled to the memory, said interrupt latency monitor including a timer and being adapted to couple to the computer and to implement the plurality of logical steps, to determine when an interrupt is asserted, assertion of the interrupt causing the computer to initiate execution of a process associated with said interrupt, said plurality of logical steps implemented by the interrupt latency monitor including:
(i) storing a temporal value in the memory that corresponds to a current value of said timer when the interrupt is asserted;
(ii) reading a current value of the timer when the computer subsequently responds to the assertion of the interrupt by initiating an interrupt service routine;
and
(iii) determining a latency value for the interrupt that corresponds to a difference between the temporal value stored in the memory and the current value of the timer read when the computer initiates the interrupt service routine, said latency value indicating the amount of time required for the computer to process the interrupt.

4 more elements

An interrupt latency monitor for monitoring interrupts asserted on a bus of a computer to which said monitor is adapted to couple, to determine an amount of time for the computer to process each of the interrupts, comprising:

(a) a timer for indicating time;
(b) a circuit for defining logical steps implemented by the interrupt latency monitor;
(c) a plurality of registers adapted to store temporal values for different interrupts asserted on the computer;
(d) a buffer circuit for detecting and temporarily storing each interrupt asserted on the bus, and for formatting the interrupts in a format required for processing by the interrupt latency monitor;
and
(e) a logic device that responds to detection of an interrupt asserted on the bus by the buffer circuit and in response thereto, obtains a temporal value for the interrupt from the timer indicating a time when the interrupt was asserted on the bus, and stores the temporal value in one of the plurality of registers, said timer also indicating a time when an interrupt service routine is subsequently initiated by the computer in response to assertion of the interrupt, a difference between the temporal value stored in said one of the plurality of registers and the time when the interrupt service routine is initiated by the computer is completed indicating a latency for the interrupt.

3 more elements

Dependencies are inferred from the claim text.

Continuous monitor for interrupt latency in real time systems

Life of this patent

Continuous monitor for interrupt latency in real time systems

Life of this patent

Abstract

Claims30