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US 5,944,813 AGranted
FPGA input output buffer with registered tristate enable
AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Life of this patent
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Abstract
In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.
Claims6
An input output buffer for an FPGA, comprising:
- a pad;
- a tristate buffer optionally driving said pad and having a tristate control terminal;
- a first flip-flop providing an output signal through said tristate buffer to said pad;
- and
- a second flip-flop providing a signal to said tristate control terminal for controlling impedance of said tristate buffer.
2 more elements
Dependencies are inferred from the claim text.