US 5,943,574 AGranted

Method of fabricating 3D multilayer semiconductor circuits

AssigneeMotorola, Inc.

InventorsSaied N. Tehrani, Kumar Shiralagi, Herbert Goronkin

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Claims16

Dependent claims

A method of fabricating three-dimensional semiconductor circuits comprising the steps of:

providing a first electrically conductive layer having a doped polysilicon layer positioned thereon and patterned into submicron geometries including first terminals of a first plurality of semiconductor devices, the doped polysilicon layer including grains;
annealing the doped polysilicon layer to expand the grains to avoid grain boundaries within a conductive portion of each of the first terminal semiconductor contacts;
forming insulated gate contacts spaced vertically from the first terminals of the first plurality of semiconductor devices so as to define vertical vias with the conductive portion of each of the first terminal semiconductor contacts providing a lower surface of one each of the vias;
depositing polysilicon including grains on the conductive portion of each of the first terminal semiconductor contacts in the vias to form conduction channels for the first plurality of semiconductor devices, an upper portion of the polysilicon in the vias being doped to form second terminal semiconductor contacts for the first plurality of semiconductor devices;
annealing the polysilicon conduction channels and the polysilicon second terminal semiconductor contacts to expand the grains to avoid grain boundaries within a conductive portion of each of the conduction channels and the second terminal semiconductor contacts;
and
depositing and patterning a second electrically conductive layer on the second terminal semiconductor contacts to define second terminals of the first plurality of semiconductor devices.

4 more elements

A method of fabricating three-dimensional semiconductor circuits comprising the steps of:

providing a substrate;
depositing a first electrically conductive layer on the substrate;
depositing a doped polysilicon layer having grains on the first electrically conductive layer;
depositing a first insulative layer on the doped polysilicon layer;
patterning the first electrically conductive layer, the doped polysilicon layer, and the first insulative layer into submicron geometries including first terminals of a first plurality of semiconductor devices;
annealing the patterned doped polysilicon layer to expand the grains to avoid grain boundaries within a conductive portion of each of the first terminals of the first plurality of semiconductor devices;
depositing and planarizing a dielectric layer over the submicron geometries;
depositing a polysilicon gate contact layer on the dielectric layer;
depositing a second insulative layer on the polysilicon gate contact layer;
opening vias through the second insulative layer, the polysilicon gate contact layer, and the dielectric layer to the first insulative layer, the vias defining conduction channels for the first plurality of semiconductor devices;
oxidizing exposed portions of the polysilicon gate contact layer within the vias to form a gate dielectric layer;
removing the first insulative layer within the vias to expose the conductive portion of each of the first terminals within each of the vias;
depositing polysilicon with grains on the conductive portion of the first terminal semiconductor contacts in each of the vias to form the conduction channels for the first plurality of semiconductor devices;
doping a top portion of the polysilicon in the vias to form second terminal semiconductor contacts for the first plurality of semiconductor devices;
annealing the polysilicon conduction channels and the polysilicon second terminal semiconductor contacts to expand the grains to avoid grain boundaries within a conductive portion of each of the conduction channels and the second terminal semiconductor contacts;
and
depositing and patterning a second electrically conductive layer on the second terminal semiconductor contacts to define second terminals of the first plurality of semiconductor devices.

14 more elements

Dependencies are inferred from the claim text.