US 5,943,382 AGranted

Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop

AssigneeNeoMagic Corp.

InventorsHung-Sung Li, Mangesh S. Pimpalkhare

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Abstract

A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons. The modulated voltage is generated by a waveform generator in the slave loop. The waveform generator is controlled by a feedback divider that also controls when phase comparison is performed. The amplitude of the waveform is adjusted to track the control voltage of the master PLL by comparing the control voltage to the modulated voltage, but only at the beginning of the modulation cycle. The modulation amplitude is kept constant over different supply voltages, ambient temperatures, and process corners.

Claims20

Dependent claims

A modulated clock generator comprising:

a master phase-locked loop (PLL), receiving a reference clock and outputting a modulated clock, the master PLL comprising:
a feedback divider, receiving the modulated clock, for generating a pulse after every M cycles of the modulated clock;
a phase comparator, receiving the reference clock and the pulse from the feedback divider, for comparing a phase of the reference clock to a phase of the pulse when the pulse is received, the phase comparator outputting a phase-difference signal;
a summer, receiving the phase-difference signal from the phase comparator, for combining a modulated signal with the phase-difference signal to generate a frequency-determining signal;
a frequency generator for generating the modulated clock having a frequency determined by the frequency-determining signal from the summer, the frequency varying over time when the modulated signal varies over time;
and
a slave voltage-locked loop (VLL) comprising:
a waveform generator, coupled to the feedback divider, for generating the modulated signal to the summer in the master PLL, the modulated signal being synchronized to the pulse from the feedback divider;
a slave comparator, receiving the phase-difference signal from the phase comparator and receiving the modulated signal from the waveform generator, for outputting a difference signal when the phase-difference signal has a same voltage as the modulated signal;
a second phase comparator, coupled to supply a level signal to the waveform generator, for comparing the difference signal from the slave comparator to the pulse from the feedback divider when the pulse is received,
whereby the slave VLL generates the modulated signal for the master PLL.

8 more elements

A clock generator for generating a frequency-modulated output clock, the clock generator comprising:

a master phase-locked loop (PLL) comprising:
a voltage-controlled oscillator (VCO), receiving a summed voltage, for outputting the output clock having an instantaneous frequency determined by the summed voltage;
a feedback divider, receiving the output clock from the VCO, for dividing a frequency of the output clock to generate a feedback clock;
a master phase comparator, receiving a reference clock having a fixed reference frequency, for comparing a phase of the reference clock to a phase of the feedback clock, the master phase comparator outputting a phase-difference signal;
a loop filter including a capacitor, the loop filter outputting a control voltage;
a master charge pump, receiving the phase-difference signal from the master phase comparator, for charging and discharging the capacitor in the loop filter in response to the phase-difference signal;
a summer, receiving the control voltage from the loop filter and receiving a modulated voltage, for outputting the summed voltage as a combination of the control voltage and the modulated voltage;
and
a slave voltage-locked loop (VLL) comprising:
a modulation generator, coupled and synchronized to the feedback divider, for generating the modulated voltage having voltage modulations in a modulation cycle;
a voltage comparator for comparing the modulated voltage to the control voltage from the master PLL and outputting a voltage pulse when the modulated voltage is equal to the control voltage;
a slave phase comparator, coupled to the voltage comparator and receiving the feedback clock, for generating a slave phase-difference signal;
a slave loop filter that includes a capacitor, the slave loop filter coupled to the modulation generator;
a slave charge pump, receiving the slave phase-difference signal, for charging and discharging the slave loop filter in response to the slave phase-difference signal;
whereby modulation is isolated from the loop filter of the master PLL by the slave VLL that generated the modulated voltage.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/990,899Filed 15 Dec 1997 · continuation in part
Priority: 21 Aug 1996
Granted: 24 Aug 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 5/18
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators: timing circuits for…
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H05K 9/0069
Screening of apparatus or components against electric or magnetic fields: methods for measuring the shielding efficiency; Apparatus therefor;…