Video/graphics memory system

A video/graphics system comprising:

• a processor for generating graphics data representative of a graphics-based image;
• a video signal port through which video data representative of a video image and graphics data are transferred bidirectionally;
• a memory assembly, said memory assembly including:
• a random access memory having multiple data locations in which graphics data and video data are selectively stored, a random access port through which data are selectively written to and read from said data locations and a serial access port through which graphics data and video data contained in said data locations are read from said random access memory;
• a host port connected to said processor for receiving graphics data therefrom;
• an auxiliary port coupled to said video signal port for receiving video data therefrom through which the video data and graphics data are exchanged bidirectionally with the video signal port;
• and
• an arbitrating multiplexer connected on a first side thereof to said host port and to said auxiliary port and on a second side thereof to said random access port of said random access memory, said arbitrating multiplexer being configured to selectively connect said host port and said auxiliary port to said random access port of said random access memory through time-multiplexed access so that said graphics data from said processor and video data from said video signal port can be written to said random access memory and graphics data and video data can be read from said random access memory to said video signal port;
• and
• an output signal port connected to said serial access port of said random access memory for receiving an integrated stream of graphics data and video data, said output signal port functioning as a port over which the integrated stream of graphics data and video data is supplied to an external display device.

A video/graphics system comprising:

• a processor for generating graphics data representative of a graphics-based image;
• a video signal port for receiving video data representative of a video image;
• a serial access port through which an integrated stream of graphics data and video data can be forwarded to an external display device;
• and
• a memory assembly, said memory assembly including:
• at least one random access memory with multiple data locations, said data locations being used to selectively store both graphics data and video data and a random access port through which graphics data and video data are written to and read from the said data locations;
• a host port, said host port being connected to said processor to allow the transfer of graphics data from said processor to said memory assembly;
• an auxiliary port, said auxiliary port being connected to said video signal port to allow the transfer of video data to said memory assembly;
• an arbitrating multiplexer connected at a first end to said host port, said auxiliary port and said serial access port and at a second end to said random access port of said random access memory, said arbitrating multiplexer being configured to provide time-multiplexed access to said random access port of said random access memory so that graphics data from said processor and video data received from said video signal port can be selectively written to said data locations of said random access memory and graphics data and video data can be read from said data locations of said random access memory through said serial access port.

In a video/graphics system comprising a processor for generating graphics data, a video signal port for receiving video data, and a display signal output port over which an integrated stream of video data and graphics data is output and a memory means, said memory means comprising:

• at least one random access memory with multiple data locations and having a first random access port, said data locations in said random access memory being able to store selectively both graphics data from said processor and video data;
• a second random access port, said second random access port being selectively coupled to said first random access port for connecting said random access memory to said processor for the transfer of graphics data;
• a serial access port, said serial access port of said memory means being coupled to said random access memory for connecting said random access memory to said display signal output port for the transfer of video data and graphics data to said display signal output port for forwarding to an external display device;
• an auxiliary port, said auxiliary port of said memory means being coupled to said random access memory for connecting said video signal port to said random access memory for the transfer of video data;
• and
• an arbitrating multiplexer coupled between said first random access port, said second random access port and said auxiliary port, whereby both said second random access port and said auxiliary port have time-multiplexed access to said first random access port of said random access memory through said arbitrating multiplexer, said arbitrating multiplexer including:
• a data multiplexer having a first end coupled to receive data from said second random access port, and from said auxiliary port and a second end coupled to said first random access port, said data multiplexer being configured to connect either said second random access port or said auxiliary port to said first random access port;
• and
• a hold circuit connected to said second random access port for monitoring when requests to write to said random access memory are received over said second random access port and connected to said data multiplexer for controlling which of said second random access port or said auxiliary port is connected to said first random access port, wherein when a write request is received over said second random access port, said hold circuit interrupts any data transfer occurring between said auxiliary port and said first random access port and directs said data multiplexer to connect said second random access port to said first random access port.

In a video/graphics system comprising a processor for generating graphics data, a video signal port for receiving video data, and a display signal output port over which an integrated stream of video data and graphics data is output and a memory means, said memory means comprising:

• at least one random access memory with multiple data locations and having a first random access port, said data locations in said random access memory being able to store selectively both graphics data from said processor and video data;
• a second random access port, said second random access port being selectively coupled to said first random access for connecting said random access memory to said processor for the transfer of graphics data;
• a serial access port, said serial access port of said memory means being coupled to said random access memory for connecting said random access memory to said display signal output port for the transfer of video data and graphics data to said display signal output port for forwarding to an external display device;
• an auxiliary port, said auxiliary port of said memory means being coupled to said random access memory for connecting said video signal port to said random access memory for the transfer of video data;
• and
• an arbitrating multiplexer coupled on one side to said first random access port and on a second side to said second random access port, said serial access port and said auxiliary port, whereby said second random access port, said serial port and said auxiliary port have time-multiplexed access to said first random access port of said random access memory through said arbitrating multiplexer.

A video/graphics system comprising:

• a processor for generating graphics data representative of a graphics-based image;
• a video signal port for receiving video data representative of a video image;
• a memory assembly, said memory assembly including:
• a random access memory having multiple data locations in which graphics data and video data are selectively stored, a random access port through which data are written to said data locations and a serial access port through which graphics data and video data contained in said data locations are read from said random access memory;
• a host port connected to said processor for receiving graphics data therefrom;
• an auxiliary port coupled to said video signal port for receiving video data therefrom;
• and
• an arbitrating multiplexer connected on a first side thereof to said host port and to said auxiliary port and on a second side thereof to said random access port of said random access memory, said arbitrating multiplexer including:
• a data multiplexer having a first end coupled to receive data from said host port and from said auxiliary port and a second end coupled to said random access port, said data multiplexer being configured to connect either said host port or said auxiliary port of said to said random access port;
• and
• a hold circuit connected to said host port for monitoring when requests to write to said random access memory are received over said host port and connected to said data multiplexer for controlling which of said host port or said auxiliary port is connected to said first random access port, wherein when a write request is received over said host port, said hold circuit interrupts any data transfer occurring between said auxiliary port and said first random access port and directs said data multiplexer to connect said host port to said first random access port;
• and
• an output signal port connected to said serial access port of said random access memory for receiving an integrated stream of graphics data and video data, said output signal port functioning as a port over which the integrated stream of graphics data and video data is supplied to an external display device.