Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal

In an integrated circuit having a plurality of internal circuits receiving a clock signal coupled to the internal circuits from an external clock signal, the clock signal coupled to the internal circuits being delayed relative to the external clock signal, a clock circuit for generating from the delayed external clock signal an internal clock signal that is synchronized to the external clock signal, comprising:

• voltage controlled oscillator means for generating a VCO output signal having a frequency determined by a frequency control signal, the internal clock signal being derived from the VCO output signal;
• phase detector means for receiving the delayed external clock signal and the VCO output signal and for generating an error signal corresponding to the difference in phase between the delayed external clock signal and the VCO output signal;
• differential amplifier means for receiving the error signal and a phase adjustment signal and for generating an output signal corresponding to the combination of the error signal and the phase adjustment signal, the phase adjustment signal corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal;
• and
• loop filter means for receiving the output signal from the differential amplifier, the loop filter means generating the frequency control signal from the differential amplifier output signal, the voltage controlled oscillator means, phase detector means, differential amplifier means, and loop filter means being connected as a phase-lock loop so that the internal clock signal is synchronized to the external clock signal.

A dynamic random access memory receiving an external clock signal, comprising:

• a plurality of first dynamic random access memory circuits to which the external clock signal is coupled, the external clock signal being delayed as it is coupled to the dynamic random access memory circuits so that the first dynamic random access memory circuits receive a delayed external clock signal;
• a second dynamic random access memory circuit adapted to receive an internal clock signal that is synchronized to the external clock signal;
• a phase-lock loop generating the internal clock signal, the phase-lock loop including a phase detector receiving the delayed external clock signal and the internal clock signal and controlling the frequency of the internal clock signal responsive to the difference in phase between the delayed external clock signal and the internal clock signal;
• and
• an offset circuit producing a predetermined offset between the phase of the internal clock signal and the phase of the delayed external clock signal when the phase-lock loop is locked, the predetermined offset corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal so that the phase of the internal clock signal is substantially the same as the phase of the external clock signal.

A method of generating an internal clock signal synchronized to an external clock signal that is coupled to a plurality of circuits in an integrated circuit, the external clock signal being delayed as it is coupled to the circuits so that the circuits receive a delayed external clock signal, the method comprising:

• comparing the phase of the delayed external clock signal to the phase of the internal clock signal;
• offsetting the comparison of the phase of the delayed external clock signal to the phase of the internal clock signal by a phase offset corresponding to the difference between the phase of the external clock signal and the phase of the delayed external clock signal;
• and
• generating as the internal clock signal a signal having a frequency and a phase determined by the offset comparison between the phase of the delayed external clock signal and the phase of the internal clock signal.