Immediate floating-point operand reformatting in a microprocessor

A method of operating a microprocessor to execute floating-point instructions upon floating-point operands retrieved from memory in a first precision format, and having a mantissa portion represented by a plurality of mantissa bits, an exponent portion represented by a plurality of exponent bits, and a sign indicator, comprising the steps of:

• monitoring a sequence of instructions to detect a floating-point load instruction for an operand of the first precision format;
• retrieving an operand from memory;
• placing the retrieved operand onto a first load/store bus that is coupled to an immediate operand formatter;
• operating a first path of the immediate operand formatter to communicate the sign indicator of the operand from the first load/store bus to a sign bit output, to add a bias difference value to the first bias of the exponent portion of the operand, to communicate the exponent portion resulting from the adding step to a plurality of exponent outputs greater in number than the plurality of exponent bits in the first format, and to communicate the mantissa portion to a plurality of mantissa outputs greater in number than the plurality of mantissa bits in the first format;
• responsive to the monitoring step detecting a floating-point load instruction for an operand of the first precision format onto the first load/store bus, applying the outputs of the first path of the immediate operand formatter to a floating-point execution unit;
• placing a retrieved operand in the first precision format onto a second load/store bus that is coupled to the immediate operand formatter;
• operating a second path of the immediate operand formatter to communicate the sign indicator of the operand from the second load/store bus to a sign bit output, to communicate the exponent portion to a plurality of exponent outputs greater in number than the plurality of exponent bits in the first format, and to communicate the mantissa portion to a plurality of mantissa outputs greater in number than the plurality of mantissa bits in the first format;
• responsive to the monitoring step detecting a floating-point load instruction for an operand of the first precision format on the second load/store bus, applying the outputs of the second path of the immediate operand formatter to the floating-point execution unit;
• monitoring a sequence of instructions to detect a floating-point load instruction for an operand of a second precision format, and having a mantissa portion represented by a plurality of mantissa bits, an exponent portion represented by a plurality of exponent bits, and a sign indicator, to the first and second load/store buses;
• placing the mantissa portion of the retrieved operand onto the first and second load/store buses;
• placing the exponent portion and sign indicator of the retrieved operand onto the second load store bus;
• operating a third path of the immediate operand formatter to communicate the sign indicator of the operand from the second load/store bus to a sign bit output, to communicate the exponent portion from the second load/store bus to a plurality of exponent outputs greater in number than the plurality of exponent bits in the second precision format, and to communicate the mantissa portion from the first and second load/store buses to a plurality of mantissa outputs greater in number than the plurality of mantissa bits in the second precision format;
• responsive to the monitoring step detecting a floating-point load instruction for an operand of the second precision format onto the first and second load/store buses, applying the outputs of the third path of the immediate operand formatter to the floating-point execution unit.

A method of operating a microprocessor to execute floating-point instructions upon floating-point operands retrieved from memory in a selected one of a plurality of precision formats, each precision format having a mantissa portion represented by a corresponding plurality of mantissa bits, an exponent portion represented by a corresponding plurality of exponent bits, and a sign indicator, comprising the steps of:

• monitoring a sequence of instructions to detect a floating-point load instruction for an operand;
• retrieving an operand from memory;
• placing the retrieved operand onto at least one load/store bus that is coupled to an immediate operand formatter;
• simultaneously converting bits on the at least one load/store bus from each of the plurality of precision formats into a high precision internal format having a sign indicator, an exponent portion having plurality of exponent bits greater in number than a maximum number of exponent bits in the plurality of precision formats and a mantissa portion having a plurality of mantissa bits greater in number than a maximum number of mantissa bits in the plurality of precision formats, each conversion supplying a sign bit, a plurality of exponent bits and a plurality of mantissa bits from the at least one load/store bus according to a selected one of the plurality of precision formats to corresponding bits of one output bus of a plurality of output busses equal in number to a number of the plurality of precision formats;
• responsive to the monitoring step detecting a floating-point load instruction selecting one of the output busses of the simultaneously converting step corresponding to a precision format of the operand.