Sequence error event detection and correction using fixed block digital sum codes
AssigneeSilicon Systems Research Limited
InventorMarcus Marrow
Life of this patent
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Abstract
A data receiving channel has a signal converter that converts a received signal into a digital signal. The digital signal is then applied to a Viterbi detector that will provide, as an output, a stream of digital signals that have a maximum likelihood of being accurate. Error correction is performed at the bit level through calculation of the error between the received signal and the maximum likelihood estimate signal produced by the Viterbi detector.
Claims21
A data receiving channel comprising:
- a signal converter means for converting an input signal to a converted signal having predefined characteristics;
- a Viterbi detector means for generating an output signal of data blocks with each data block having a predefined number of symbols from the converted signal;
- error correction means for detecting and correcting errors in the data blocks, said error correction means including a target channel filter means for filtering the output signal with the predefined characteristics to provide a target channel signal that is an estimate of the converted signal, and
- a comparator means for providing an error signal from a comparison of the target channel signal and the converted signal.
A method of receiving data comprising:
- converting an input signal to a converted signal having predefined characteristics;
- estimating the converted signal to provide an output signal representing an estimate data block having a predefined number of bits;
- detecting and correcting errors in the estimated data block and further including the step of encoding the data block with the predefined characteristics to provided a target channel signal that is an estimate of the converted signal;
- and
- providing an error signal by comparing the target channel signal with the converted signal.
A data receiving channel for converting a coded data signal into a digital signal and wherein the coded data signal includes a predetermined number of symbols arranged into sequential blocks and each block is encoded with predefined characteristics comprising:
- a signal converter circuit arranged to receive an input signal and to convert the input signal into a converted signal;
- a Viterbi decoder circuit operatively connected to receive the converted signal, the Viterbi decoder circuit including an estimating circuit that provides a partial-response maximum likelihood signal of data blocks with each data block having a predefined number of symbols;
- an error correction circuit including a target channel filter connected to encode the partial-response maximum likelihood signal with the predefined characteristics to provide a target channel signal that is an estimate of the converted signal, and
- a comparator that receives the target channel signal and the converted signal as inputs and compares the target channel signal with the converted signal to provide an error signal.
Dependencies are inferred from the claim text.