Register interface for flash EEPROM memory arrays
AssigneeIntel Corporation
InventorKurt B. Robinson
Life of this patent
Estimating the term…
Abstract
A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.
Claims13
A flash EEPROM memory device comprising:
- a memory array including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns,
- a query memory storing data defining characteristics of the flash storage device, and
- a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for adapting the purpose of the commands in the device based on the data, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.
A method for accessing a device including a flash EEPROM memory comprising the steps of:
- directing a query command to a register of the device,
- decoding the query command in the register,
- querying the device to determine its characteristics in flash EEPROM memory primitives,
- placing characteristics of the device in a plurality of characteristic registers of the device,
- initializing a device driver for the device using the characteristics in the characteristic registers,
- writing data to the device using the characteristics determined through a register interface providing state machines for erasing and writing to the flash EEPROM memory.
A computer system comprising:
- a central processing unit;
- main memory;
- a bus joining components of the computer system to the central processing unit and main memory;
- and
- a device joined to the bus comprising:
- a memory array including a plurality of blocks of flash EEPROM memory arranged to be accessed in rows and columns,
- a query memory storing data defining characteristics of the flash EEPROM memory, and
- a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for adapting the purpose of the commands in the device based on the data, the interface including a command register for receiving commands and a plurality of registers for providing data stored in the query memory as output.
Dependencies are inferred from the claim text.