Single-etch stop process for the manufacture of silicon-on-insulator wafers

A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

• forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and having a thickness ranging between about 0.5 .mu.m and 50 .mu.m, the oxide layer being between the device layer and the substrate layer, the device wafer having a p+ or n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,
• removing a portion of the device wafer from the silicon-on-insulator bonded wafer, the remaining portion of the device wafer having, after removal, a defect-free surface and a total thickness variation of less than about 10 .mu.m,
• immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the device wafer to expose the device layer,
• reactivating the device wafer surface, and
• polishing the exposed device layer to produce a polished silicon-on-insulator wafer.

A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

• forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a p.sup.+ or n.sup.+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,
• removing a portion of the device wafer from the silicon-on-insulator bonded wafer,
• immersing the remaining portion of the device wafer in an etchant containing hydrofluoric acid and nitric acid and further containing acetic acid or phosphoric acid, and
• after the etch rate of the device wafer begins to diminish, withdrawing the silicon-on-insulator bonded wafer from the etchant, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded wafer in the etchant.

A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

• forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a p+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,
• removing a substantial portion of the device wafer from the silicon-on-insulator bonded wafer by rough grinding,
• removing a portion of the rough ground device wafer from the silicon-on-insulator bonded wafer by fine grinding,
• removing a portion of the fine ground device wafer from the silicon-on-insulator bonded wafer by polishing, the remaining portion of the device wafer having a defect-free surface after removal, and
• immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the polished device wafer to expose the device layer.

A single-etch stop process for the manufacture of silicon-on-insulator wafers, the process comprising

• forming a silicon-on-insulator bonded wafer comprising a substrate layer, an oxide layer, a device layer, and a device wafer, the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the substrate layer, the device wafer having a n+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm,
• removing a substantial portion of the device wafer from the silicon-on-insulator bonded wafer by rough grinding,
• removing a portion of the rough ground device wafer from the silicon-on-insulator bonded wafer by fine grinding,
• removing a portion of the fine ground device wafer from the silicon-on-insulator bonded wafer by polishing, the remaining portion of the device wafer having a defect-free surface after removal, and
• immersing the silicon-on-insulator bonded wafer in an etching solution to preferentially etch the remaining portion of the polished device wafer to expose the device layer.