# US 5,936,887 A · Non-volatile memory device with NAND type cell structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,936,887 A - Document ID: US5936887A - Status: Granted - Kind: A - Application number: 08/910,025 - Filed: 1997-08-12 - Granted: 1999-08-10 - Earliest claimed: 1996-08-13 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Jung-Dal Choi; Dong-Jun Kim; Wang-Chul Shin; Jong-Han Kim - Web page: https://patentgrep.com/patent/US5936887A ## CPC - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - G11C 11/5621: {using charge storage in a floating gate} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 16/24: Bit-line control circuits - G11C 2211/5649: Multilevel memory with plate line or layer, e.g. in order to lower programming voltages - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A non-volatile memory device is disclosed in which a pair of two adjacent memory cell strings are commonly connected to one bit line and the memory cell strings are selectively driven to obtain a relatively wide pitch margin between two bit lines. The device has a conductive plate line which is located along each memory cell string or a pair of memory cell strings to drive memory cells thereof with a relatively low program voltage to a word line. The memory device comprises a plurality of memory cell strings which are arranged in parallel with one another and each of which extends in the same direction as a bit line 12, and a pair of two adjacent memory cell strings 11a and 11b are commonly connected to the bit line 12. The memory device also comprises a string selector for selecting either the first string 11a or the second string 11b in response to signals from string select lines SSL1 and SSL2, and a plurality of plate lines PLa or 21a and PLb or 21b which are respectively arranged on the first and second strings 11a and 11b. In the memory cell, if voltages having different levels are applied to the control gate of a memory cell of the string selected thus and the plate line, at least more than two coupling voltages are induced to a floating gate of a corresponding memory cell so that two bits of information can be stored in and read out of one memory cell. The memory device has a cell structure in which a pair of two adjacent memory cell strings are commonly connected to one bit line, so that margin width between two bit lines, i.e., a bit line pitch can be relatively widely obtained. ## Claims ### Claim 1 A non-volatile memory device with a multilevel cell structure, comprising: a semiconductor substrate having a main surface; a plurality of memory cell strings formed on the main surface of said semiconductor substrate, a plurality of memory cells of each memory cell string being connected in series on the main surface, and each memory cell having a floating gate for storing charges representing information and a control gate on the floating gate with a dialectic layer therebetween; an insulating layer covering said memory cell strings; and a conductive plate layer formed on said insulating layer, wherein at least two coupling voltages are induced to at least one of the plurality of floating gates when different voltages are applied to the control gate and plate layer, respectively, and thereby two bits of information are stored and read out of one memory cell. ### Claim 2 (depends on 1) The non-volatile memory device of claim 1, wherein said conductive plate layer comprises one of polysilicon and polycide. ### Claim 3 (depends on 1) The non-volatile memory device of claim 1, wherein said conductive plate layer is formed along each memory cell string and above the floating gate of each memory cell. ### Claim 4 (depends on 1) The non-volatile memory device of claim 1, wherein said conductive plate layer is formed along the pair of said two adjacent memory cell strings which are commonly connected to the bit line. ### Claim 5 (depends on 1) The non-volatile memory device of claim 1, wherein said conductive plate layer is formed along two adjacent memory cell strings between two adjacent pairs, each of which is comprised of two adjacent memory cell strings commonly connected to the bit line. ### Claim 6 (depends on 1) The non-volatile memory device of claim 1, further comprising a selecting means for selecting a group of said memory cells in each memory cell string. ### Claim 7 (depends on 6) The non-volatile memory device of claim 6, wherein said selecting means comprises a plurality of select transistors which are made of the memory cells at both ends of the memory cell string. ### Claim 8 (depends on 7) The non-volatile memory device of claim 7, wherein each of said select transistors is made of MOS type. ### Claim 9 (depends on 7) The non-volatile memory device of claim 7, wherein each of said select transistors is made of a MOS transistor in which control and floating gates of the memory cell at both ends of said memory cell string are electrically connected with each other through a contact hole to serve as a gate of said MOS transistor. ### Claim 10 A non-volatile memory device with a multilevel cell structure, comprising: a semiconductor substrate having a main surface; a plurality of memory cell strings formed on the main surface of said semiconductor substrate, a plurality of memory cells of each memory cell string being connected in series on the main surface, and each memory cell having a floating gate for storing charges representing information and a control gate on the floating gate with a dialectic layer therebetween; an insulating layer covering said memory cell strings; a conductive plate layer formed on said insulating layer; and a plurality of bit lines connected through contacts to said memory cell strings, each bit line being commonly connected to a pair of two adjacent memory cell strings of said memory cell strings, wherein at least two coupling voltages are induced to at least one of the plurality of floating gates when different voltages are applied to the control gate and plate layer, respectively, and thereby two bits of information are stored and read out of one memory cell. ### Claim 11 (depends on 10) The non-volatile memory device of claim 10, further comprising a selecting means for selecting a group of said memory cells in each memory cell string. ### Claim 12 (depends on 11) The non-volatile memory device of claim 11, wherein said selecting means comprises a plurality of select transistors which are made of the memory cells at both ends of said memory cell string. ### Claim 13 (depends on 12) The non-volatile memory device of claim 12, wherein each of said select transistors is made of MOS type. ### Claim 14 (depends on 12) The non-volatile memory device of claim 12, wherein each of said select transistors is made of a MOS transistor in which control and floating gates of the memory cell at both ends of said memory cell string are electrically connected with each other through a contact hole to serve as a gate of said MOS transistor.