US 5,936,884 A · Multiple writes per a single erase for a nonvolatile memory

Abstract

A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.m adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2.sup.m adjacent levels identified by the group indicator.

Claims19

Dependent claims

A method of writing to a memory cell comprising the steps of:

storing m bits in a first group of levels of the memory cell, wherein m is greater than or equal to two;
storing m superseding bits in a second group of levels of the memory cell, without erasing the memory cell;
and
adjusting a group indicator to identify the second group.

1 more element

Dependencies are inferred from the claim text.

Multiple writes per a single erase for a nonvolatile memory

Life of this patent

Multiple writes per a single erase for a nonvolatile memory

Life of this patent

Abstract

Claims19