US 5,936,267 A · Insulated gate thyristor

Abstract

Surfaces of a second p base region 6 and an n emitter region 8 are covered with an insulating film 19 and the second p base region 6 and a first p base region 4 are connected partially below a gate electrode 10. In a conventional EST, a potential difference is obtained by hole current flowing in a Z direction to make the transition from an IGBT mode to a thyristor mode. However, since an n emitter region 8 becomes a potential almost equal to that of an n source region 7, hole current injected from a p emitter layer 1 causes the potential of the second p base region 6 to rise, making the prompt transition to the thyristor mode. Particularly, in the portion where the second p base region 6 and the first p base region 4 are in contact with each other, an inversion layer at the gate on time is short and small in resistance and does not touch an n base layer 3, thus electrons from the n source region 7 flow effectively into the n emitter region 8 and the on-state voltage is lowered. At the turn-off time, a pn junction below the n emitter region 8 is uniformly covered, the destruction resistance amount is enhanced, and the turn-off time is shortened.

Claims10

Dependent claims

An insulated gate thyristor, comprising:

a first conductivity type base layer of high resistivity;
a first second-conductivity type base region and a second second-conductivity type base region, selectively formed in a surface layer of one face of said first conductivity type base layer;
a first conductivity type source region selectively formed in a surface layer of said first second-conductivity type base region;
a first conductivity type emitter region selectively formed in a surface layer of said second second-conductivity type base region;
a gate electrode formed via an insulating film on a surface of said first second-conductivity type base region sandwiched between said first conductivity type source region and said emitter region, an exposed portion of said first conductivity type base layer, and a surface of said second second-conductivity type base region;
a first main electrode in contact with an exposed portion of said first second-conductivity type base region and said first conductivity type source region;
a second-conductivity type emitter layer formed on an opposite face of said first conductivity type base layer;
a second main electrode in contact with said second-conductivity type emitter layer;
and
an insulating film covering a surface of said second second-conductivity type base region;
wherein said first second-conductivity type base region and said second second-conductivity type base region are connected below said gate electrode.

8 more elements

An insulated gate thyristor, comprising:

a first conductivity type base layer of high resistivity;
a first second-conductivity type base region and a second second-conductivity type base region, selectively formed in a surface layer of one face of said first conductivity type base layer;
a first conductivity type source region selectively formed in a surface layer of said first second-conductivity type base region;
a first conductivity type emitter region selectively formed in a surface layer of said second second-conductivity type base region;
a gate electrode formed via an insulating film on a surface of said first second-conductivity type base region sandwiched between said first conductivity type source region and emitter region, an exposed portion of said first conductivity type base layer, and a surface of said second second-conductivity type base region;
a first main electrode in contact with an exposed portion of said first second-conductivity type base region and said first conductivity type source region;
a second conductivity type emitter layer formed on an opposite face of said first conductivity type base layer;
a second main electrode in contact with said second conductivity type emitter layer;
and
an insulating film covering a surface of said second second-conductivity type base region;
wherein said first second-conductivity type base region and said second second-conductivity type base region are connected below said gate electrode;
wherein at least one of said first second-conductivity type base region, said second second-conductivity type base region, said first conductivity type emitter region, and said first conductivity type source region forms a polygonal shape, a circular shape, or an elliptical shape;
wherein a plurality of said first second-conductivity type base regions and a plurality of said first conductivity type source regions are formed in proximity to said second second-conductivity type base region;
wherein a substantially annular gate electrode is disposed so as to surround the insulating film on the surface of said second second-conductivity type base region;
wherein said first main electrode is disposed via an insulating film on an opposite side of said gate electrode;
wherein said first conductivity type base layer exists between two first second-conductivity type base regions and wherein said gate electrode is disposed via a gate insulating film on the surfaces of the two first second-conductivity type base regions.

13 more elements

Dependencies are inferred from the claim text.

Insulated gate thyristor

Life of this patent

Insulated gate thyristor

Life of this patent

Abstract

Claims10