US 5,933,855 AGranted

Shared, reconfigurable memory architectures for digital signal processing

OwnerRichard Rubinsteininventor

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Abstract

Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.

Claims25

Dependent claims

A memory system for use in digital signal processing comprising:

an array of memory cells;
the array of memory cells including a plurality of word lines, each word line arranged for accessing a corresponding row of the memory cells;
the array of memory cells further including a plurality of bit lines, each of the bit lines coupled to a corresponding one of the memory cells in each row of the memory cells;
switching circuitry for controllably dividing each one of the plurality of bit lines of the array to form first and second blocks of memory cells;
a first address generator for indicating a first selected one at a time of the word lines in the first and second memory blocks;
a second address generator for indicating a second selected one at a time of the word lines in the first and second memory blocks;
address switching means for coupling the first address generator to the word lines of the first memory block and the second address generator to the word lines of the second memory block responsive to a first value of a configuration control signal, and coupling the first address generator to the word lines of the second memory block and the second address generator to the word lines of the first memory block responsive to a second value of the configuration control signal;
and
a data multiplexer means for coupling the bit lines of the first memory block to a first data port and the bit lines of the second memory block to a second data port responsive to a first value of a selection control signal and coupling the bit lines of the first memory block to the second data port and the bit lines of the second memory block to the first data port responsive to a second value of the selection control signal.

6 more elements

A memory system for use in digital signal processing comprising:

an array of memory cells;
the array of memory cells including a plurality of word lines, each word line arranged for accessing a corresponding row of the array;
the array of memory cells further including a plurality of bit lines, each of the bit lines coupled to a corresponding one of the memory cells in each row of the array;
switching circuitry for dividing each one of the plurality of bit lines of the array to form first and second blocks of memory cells;
a first address generator for indicating a selected one at a time of the word lines in the first and second memory blocks;
a second address generator for indicating a selected one at a time of the word lines in the first and second memory blocks;
and
means for coupling a first selected one at a time of the first and second address generators to the first memory block of the array so as to assert the word line in the first memory block indicated by the first selected address generator and a second selected one at a time of the first and second address generators to the second memory block of the array so as to assert the word line in the second memory block indicated by the second selected address generator, the coupling means being arranged to select said first and second selected ones of the first and second address generators in response to an address select control signal;
first input means for receiving one or more bits of write data from a first data source;
second input means for receiving one or more bits of write data from a second data source;
and
data multiplexer means for coupling a first selected one at a time of the first and second input means to the bit lines of the first memory block for writing data into the first memory block from the corresponding data source and coupling a second selected one at a time of the first and second input means to the bit lines of the second memory block for writing data into the second memory block from the corresponding data source, the input control means being arranged to select said first and second data ones of the first and second input means in response to a data source select control signal.

9 more elements

A method for continuous execution of multiple processes in a single memory array, the method comprising the steps of:

providing a contiguous series of segments of memory cells forming the memory array;
configuring a first contiguous set of the segments to form a first block of memory;
configuring a second contiguous set of the segments non-overlapping the first set, to form a second block of memory;
executing a first process in the first block of memory;
executing a second process in the second block of memory;
swapping the first and second blocks of memory;
continuing execution of the second process in the first block of memory;
and
continuing execution of the first process in the second block of memory;
repeating said swapping and both continuing steps so that the first and second processes operate substantially continuously.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/821,326Filed 21 Mar 1997
Granted: 3 Aug 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G11C 8/10
Arrangements for selecting an address in a digital store: decoders
G05B 19/042
Program control other than numerical control, i.e. in sequence controllers or logic controllers: using digital processors
G06F 12/0284
User address space allocation, e.g. contiguous or non contiguous base addressing: multiple user address space allocation, e.g. using different…
H04N 19/61
Using transform coding: in combination with predictive coding